i think maybe i asked this before but did not get an answer ...

i recently made a mistake (first one ever)

i 'improved' a working design on a rev spin by slightly increasing power plane voids under 1.4GHz signal traces and input filters

i did not catch that the void (primitives on power planes) intersected a tiny via tagged on the side of an 0603 resistor and thus spoiled the gnd connection to the resistor (actually a tiny bit appeared to connect but was probably not fabricate-able)

as is well known the 99SE DRC does not flag this other than a generalized warning to which i am now well immune since i always have primitives on all planes

upon explaining this to my associate he was amazed that such an important DRC function was missing from protel since he said that PADs has had that for many many years including something about 'amount of copper connection' which part i did not quite catch **

so the question is, does DXP/Protel 2004 finally address this critical need ?

ds

**
a bit more blather along the sames lines ...

on this same board there is an area where i have ground 'cuts'
(not 'splits', but rather traces on the planes to localize circulating currents) i noticed (in time in this case) that there was an area which had very limited plane continuity remaining after the late addition of a mounting hole near a 'cut' in the plane so even if protel had a negative continuity plane check, this would have passed but would have been a crappy situation

the PADs 'minimum amount of copper' DRC implied by my friend would have flagged such a situation
does Protel 2004 address this ? or are there plans to ?

would this also apply to the situation of a rounded track end just barely grazing the edge of a pad which passes protel continuity but would probably fab as a break?


_______________________________________________________________________
Integrated Controls, Inc.           Tel: 415-647-0480  EXT 107
2851 21st Street                    Fax: 415-647-3003
San Francisco, CA 94110             www.integratedcontrolsinc.com


Brad Velander wrote:
Leo,
        Yes I have seen this issue as well, wrecked a board or two over the 
years. It is some bug that seems to be particular to specific detailed 
geometries in a poured polygon area. I am assuming that you have a polygon 
where this shows up, it has always been such on my designs. It may effect 
planes under certain circumstances but I have never seen it there because I 
barely ever use true planes.
        The only fix that I have found is to tweak the polygon outline slightly 
in the area effected. Move the polygon vertices by some small amount and then 
repour. It seems to usually occur near a vertice for the polygon outline or 
where you have a vertice for a cutout or clearance area (watch for small tight 
acute angles on the polygon pour outline, cutout or just how the polygon has 
poured with the clearance rule). So moving the polygon or a cutout vertice just 
slightly (+/-5mils - +/- 50mils) seems to fix it. You may have to try a couple 
of different vertice moves until the Gerber comes out correct. Another option 
is to vary the clearance (even as little as +/-1 mil) for that polygon as well 
so that the actual poured polygon edges have been moved slightly.

Sincerely,
Brad Velander
Senior PCB Designer
Northern Airborne Technology
#14 - 1925 Kirschner Road,
Kelowna, BC, V1Y 4N7.
tel (250) 763-2329 ext. 225
fax (250) 762-3374



-----Original Message-----
From: Leo Potjewijd [mailto:[EMAIL PROTECTED]
Sent: Monday, September 19, 2005 5:31 AM
To: [email protected]
Subject: [PEDA] arcs in Gerber go the wrong way


On the PCB (P99SE) all my arcs look great, even on the print preview.
But in the Gerber files some, not all, are wrong: the start and end in the right places, but go the wrong way around. So a 90 degree turn ends up as a 270 degree turn with another center and shorts stuff......

It happened once before, but the fab house detected and reported that error so they could correct it in time. Like now, I could not identify the source of the problem and have no clue whatsoever....

I checked the PCB at ASCII level but could not find any indications what went wrong (a 'good' one looks exactly the same as a 'wrong' one). I even generated the Gerbers from that copy: no luck. Inside the Gerbers I am at a loss: I cannot identify arcs, let alone the right and wrong ones.

Has anyone seen this before and found a solution or workaround?
Checking the 'software arcs' box is not an option: that messes up the already tight clearances (had a close shave with that one, too).....


Leo Potjewijd
hardware designer
Integrated Engineering B.V.

[EMAIL PROTECTED]
+31 20 4620700

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