QFN packages are a bit tough - more on this in a sec. But as to the part, if you create a FP with tracks/fills and such, you have to update nets from connected copper, otherwise it gets weird and will DRC error on ya... I think that's what you mean... please correct me if I'm wrong.
When you go Design - Netlist Manager you get a Net list manager box. On the bottom left there's a button called Menu. Click that and the flyout has entry for " Update Free Primitives From Component Pads. As to the thermal pad underneath, a few things: I usually use a big square pad called TG or something like that. It will give you a stencil and soldermask so you won't have to do it manually with fills/pours - - BUTTT Big Butt here (like big butts - sometimes) There's a bunch o stuff going on about MLF/QFN thermal pads and issues with surface tension during reflow. Basically, the large pad paste mask/stencil opening can sometimes prohibit the part from proper reflow of the stenciled/paste laden smaller pads. Here's a link I found concerning this http://www.screami ngcircuits.com/Portals/0/documents/QFN%20Layout%20Guidelines.pdf He calls it QFN float. I've had this issue before, with QFN's kinda floating. So what I did (at least in Altium Designer) In the PCB lib editor: I made it so the big pad I use has a pastemask override of something silly negative, like -200 mils (similar to tenting) then I manually add the proper smaller matrix of squares on the paste mask layer, to give the rec 50% coverage and size the squares to be consistant with the outer pads. I then , when doing the layout, add the stitching vias to the pad for the proper thermal connection to ground planes/bot side pour. I checked this in a test with a independent gerber viewer and it seems to work.... I hope this makes sense - I suck at typing. In a message dated 5/3/2007 4:41:30 PM Eastern Daylight Time, [EMAIL PROTECTED] writes: > > I have a QFN-10 footprint that I am creating. > > The data sheet shows a solder pad under the device (fill), 5 vias and 4 > tracks all used for heat sinking. > > I placed a copper fill on the PCB component and placed 5 pads and tracks as > shown in the data sheet. The 5 pads have designators that refer to 5 pins in > the schematic component. > > The 5 pins all connect to GND. When I place the PCB part and pour a polygon > GND it does not pick up on the fact that the fill, 5 pads and tracks are to > be connected to GND. > > Is this the correct approach? ************************************** See what's free at http://www.aol.com. ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[EMAIL PROTECTED] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
