"Black Pad Disease" is a fabrication failure in which the immersion gold process compromises the nickel under coat in a locallized hypercorrosive process state. It is sensitive to a number of parameters in the plating processes including temperature, pH, time, circulation, galvanics, alloy composition, and impurities (such as monomers from undercured mask). During Ni deposition, some P (Phosphorus) is included in the alloy (for various intentional reasons). During the Au (Gold) plating process Au atoms are exchanged for Ni (Nickel) atoms, causing the P to be enriched while the Ni is depleted at the junction. If this goes too far too fast, there may be too little Ni present to form the Ni/Sn (Nickel/Tin) intermetallics at the junction necessary to bond the solder properly. When this weak bond breaks (usually due to thermal expansion effects upon bonded materials with differing thermal coefficients of expansion) there will be a failure. The problem is worst under large chips with fine pitch(such as BGAs) where such forces concentrate around the outer pads. Either too much or too little P can aggrivate the problem, as can underdeveloped photomask, any positive galvanic action on the pin, and a myriad of other things.
The following new criteria and/or tests are what I have found to be suggested to help detect and/or prevent this from occurring: 1) Increase Ni plating > 100u". It could be >160u" to make a less nodular surface (hyper-corrosion begins in nodular boundaries in the Ni) 2) Ni Plating should have a minimum P content of 7% if using conventional immersion gold. (This is for the fab house reference. I only specify the boards be free from black pads in a destructive sampling inspection (see 8 below)) 3) Ni Plating should also have a consistent deposition rate. (This is also for board house reference.) 4) Ni Plating should have a specially designed stabiling system for long down times. (This is also for board house reference.) 5) Decrease Au plating to 2u"<Au<4u" (.05-.1um). 6) Better cure the solder mask before ENIG plating. (This is also for board house reference house, along with numerous process cleanliness and control items.) 7) Low vacuum SEM + EDX can be used to nondestructively inspect (but this is expensive). 8) Simple optical inspection of Ni on the pads of samples (after Cyanide etching the Au off) can quickly show to what extent this may have been occurring during a particular PCB ENIG run. (This is much less expensive.) A new immersion gold process has been developed which combines Ni displacement with an autocatalytic reaction which minimizes Ni corrosion and allowing lower P in the Ni. This should be looked into by the board house. Runaway gold plating (hyper-corrosion) is evidenced by increased Au thickness on individual pads. Positive external voltages applied to a pad have been shown to induce hyper-corrosion in the Au plating process of that particular pad. There is evidence to suggest that electrically interconnected pads in different locations and of different exposed area are more susceptable to onset of such hyper-corrosion. A suggested hypothesis for this is that localized variations in the plating solution (such as locallized depletion) or other conditions may induce a small differential galvanic charge which triggers hyper-corrosion. Once the hyper-corrosion starts it may generate chemical conditions which make the hyper-corrosion self-supporting. Thicker Au on corroded pads is consistent with this. Better stirring in the plating bath has been suggested to help prevent this triggering. There hase been some talk of a special conductive plating to equalize all panel potentials during ENIG, but I don't have details on this. Regards, Jeff ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:PEDA@techservinc.com Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[EMAIL PROTECTED] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/peda@techservinc.com
