Andreas Portele wrote:
"P-state change" looks like AMD's "Cool'n Quiet", right? Are there any plans to support it in the near future?
It is a very nice feature for mostly idling servers (and word processors ;) )
We're working on this. Basic support is not difficult, but making this work on
an
MP and keeping the TSC counters close enough (Solaris needs a inexpensive
source of
monotonic hi-resolution timestamps) is "tricky", since TSC frequency varies
with PSTATE.
One does, after all, want to be able to control the various CPUs P-states
independently
as powering up all CPUs on a large machine because someone is busy with a
single CPU
is quite inefficient.
The ideal chip for Solaris from a time perspective has a hardware-synchonized
hi-resolution invarient frequency time stamp counter on each CPU, with a
programmable count-down one-shot timer that generates high level interrupts
to match.
- Bart
--
Bart Smaalders Solaris Kernel Performance
[EMAIL PROTECTED] http://blogs.sun.com/barts
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