> Doesn't matter. Could even be dedicated > point-to-point links between all chips. My > assumption is that a processor on a chip can access > the memory controller without sending messages to > other chips via the xbar/hypertransport links. Of > course this can't be done naively...
Right. The reason I ask, is that in a 4 node ring you have a 3 level latency topology (local/either neighbor/far node) vs 2 level where there is only local and remote. -Eric This message posted from opensolaris.org _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
