On 4/26/07, Brian Gupta <[EMAIL PROTECTED]> wrote:
Future of x86
With each extra core we are seeing more wasted heat and energy go into
missed branches of execution.
With the AMD PowerNow technology, the cores you aren't using get
turned off, and low utilization they reduce the clock rate. How this
appears in the system performance monitoring utilities is actually a
more interesting question for this email alias.
What I want is to have the per-core cycle hardware counter surfaced as
a standard metric in the per-cpu kstat, then I can tell how many clock
cycles that core had over a time interval, and use that in the
calculation of %busy.
What is the answer? 1000+ core count massively parallel microprocessors,
that are based on a modified 486 core.
I don't see how that helps the question you pose above.
Assuming .65 nm process you could actually get to 4000+ cores on a single
piece of silicon today.
Azul have 96 cores of 64bit java engine per socket.
What are your thoughts regarding scaling Solaris to thousands of
cores within the next couple of years?
I think its more interesting to leverage commodity technology, such as
the billions of low power mobile device CPUs that can run ARM/Linux.
The market for chips with huge numbers of CPUs per chip is too small
to compete. The enterprise sweet spot is in the current scaling range
of Solaris i.e. 32-128 CPUs, I don't see that increasing by another
order of magnitude.
Adrian
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