Nicolas Michael wrote: > trapstat -T is not working properly: It only reports some tsb misses, > but the columns for tlb misses are all 0 (instruction and data).
This is the expected result. The T2 processor handles TLB misses in hardware, by accessing the TSB directly. If the mapping is not found in the TSB, then a software handler is invoked, and you see the TSB miss in trapstat. If the mapping *is* found in the TSB, then software is not involved, hence trapstat cannot see the event. This feature is called hardware tablewalk (HWTW). The good news is that the cost of TLB misses is reduced. The downside is that you lose visibility into which page sizes cause the misses. You can use "pmap -s" to see what page sizes are used in your processes, and if you see a large range of 8K pages, use large pages and see if the TLB miss rate that you measure with hardware counters goes down. You can also use the hardware counters to estimate if the "high" TLB miss rate really matters. TLB misses that hit in the TSB and hit in the L2$ are very cheap - approx 25 cycles. The hardware counters tell you how many TLB misses miss in the L2 - see the countes ITLB_HWTW_miss_L2 and DTLB_HWTW_miss_L2. - Steve Sistare _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
