Hello, On Wed, Apr 2, 2008 at 1:04 PM, J K Rai <[EMAIL PROTECTED]> wrote: > Thanks Dan And Stephen > > I want to sample no. of accesses on TLB (I+D) and L2 cache misses > simultaneously for a given process / thread. > > You said Pentium4 is complex. What's about xeon (single core and quad core) > as well as core2quad? > > If you have an Intel Core 2, then use this. It is much better and easier to program and the libpfm support is in much better shape than for Pentium 4. Note that you'd have to find the equivalent events.
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