This is version 2. Enclosed the diff to the first version.
-Robert
diff --git a/include/perfmon/pfmlib_amd64.h b/include/perfmon/pfmlib_amd64.h
index 4ce4fa3..223790d 100644
--- a/include/perfmon/pfmlib_amd64.h
+++ b/include/perfmon/pfmlib_amd64.h
@@ -174,12 +174,30 @@ typedef struct {
#define PFM_AMD64_SEL_GUEST 0x4 /* guest only */
#define PFM_AMD64_SEL_HOST 0x8 /* host only */
+/*
+ * AMD-specific input parameters
+ */
+
+/*
+ * IBS input parameters
+ *
+ * Maxcnt specifies the maximum count value of the periodic counter,
+ * 20 bits, bits 3:0 are always set to zero.
+ */
+
+typedef struct {
+ unsigned int maxcnt; /* 20 bits, */
+ unsigned int options;
+} ibs_param_t;
+
+#define IBS_OPTIONS_RANDEN 1 /* enable randomization (IBS fetch only) */
+
typedef struct {
pfmlib_amd64_counter_t pfp_amd64_counters[PMU_AMD64_MAX_COUNTERS]; /*
extended counter features */
uint32_t flags; /* use flags */
uint32_t reserved1; /* for future use */
- ibsfetchctl_t ibsfetchctl; /* IBS fetch control */
- ibsopctl_t ibsopctl; /* IBS execution control */
+ ibs_param_t ibsfetch; /* IBS fetch control */
+ ibs_param_t ibsop; /* IBS execution control */
uint64_t reserved2; /* for future use */
} pfmlib_amd64_input_param_t;
@@ -187,6 +205,13 @@ typedef struct {
#define PFMLIB_AMD64_USE_IBSFETCH 1
#define PFMLIB_AMD64_USE_IBSOP 2
+/*
+ * AMD-specific output parameters
+ *
+ * The values ibsfetch_base and ibsop_base pass back the index of the
+ * ibsopctl and ibsfetchctl register in pfp_pmds[].
+ */
+
typedef struct {
uint32_t ibsfetch_base; /* Perfmon2 base register index */
uint32_t ibsop_base; /* Perfmon2 base register index */
diff --git a/lib/pfmlib_amd64.c b/lib/pfmlib_amd64.c
index d6767ca..3cd5ffc 100644
--- a/lib/pfmlib_amd64.c
+++ b/lib/pfmlib_amd64.c
@@ -433,6 +433,8 @@ static int pfm_amd64_dispatch_ibs(
pfmlib_output_param_t *outp, pfmlib_amd64_output_param_t *outp_mod)
{
unsigned int pmc_base, pmd_base;
+ ibsfetchctl_t ibsfetchctl;
+ ibsopctl_t ibsopctl;
if (!inp_mod || !outp || !outp_mod)
return PFMLIB_ERR_INVAL;
@@ -450,7 +452,12 @@ static int pfm_amd64_dispatch_ibs(
pmc_base = outp->pfp_pmc_count;
pmd_base = outp->pfp_pmd_count;
outp->pfp_pmcs[pmc_base].reg_num = PMU_AMD64_IBSFETCHCTL_PMC;
- outp->pfp_pmcs[pmc_base].reg_value = inp_mod->ibsfetchctl.val;
+ ibsfetchctl.val = 0;
+ ibsfetchctl.reg.ibsfetchen = 1;
+ ibsfetchctl.reg.ibsfetchmaxcnt = inp_mod->ibsfetch.maxcnt >> 4;
+ if (inp_mod->ibsfetch.options & IBS_OPTIONS_RANDEN)
+ ibsfetchctl.reg.ibsranden = 1;
+ outp->pfp_pmcs[pmc_base].reg_value = ibsfetchctl.val;
outp->pfp_pmds[pmd_base].reg_num = PMU_AMD64_IBSFETCHCTL_PMD;
outp_mod->ibsfetch_base = pmd_base;
++outp->pfp_pmc_count;
@@ -467,7 +474,10 @@ static int pfm_amd64_dispatch_ibs(
pmc_base = outp->pfp_pmc_count;
pmd_base = outp->pfp_pmd_count;
outp->pfp_pmcs[pmc_base].reg_num = PMU_AMD64_IBSOPCTL_PMC;
- outp->pfp_pmcs[pmc_base].reg_value = inp_mod->ibsopctl.val;
+ ibsopctl.val = 0;
+ ibsopctl.reg.ibsopen = 1;
+ ibsopctl.reg.ibsopmaxcnt = inp_mod->ibsop.maxcnt >> 4;
+ outp->pfp_pmcs[pmc_base].reg_value = ibsopctl.val;
outp->pfp_pmds[pmd_base].reg_num = PMU_AMD64_IBSOPCTL_PMD;
outp_mod->ibsop_base = pmd_base;
++outp->pfp_pmc_count;
--
Advanced Micro Devices, Inc.
Operating System Research Center
email: [EMAIL PROTECTED]
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