Robert,
There is a problem with this part of the patch.
It modifies heavily smpboot_64.c and cpufeature_32.h.
Perfmon patches those files but the changes proposed here
are beyond the changes made by perfmon. I think you should
first submit the cleanup for the unmodified files, Then I will pick
them up. Otherwise, I be maintaining a file that is way out-of-sync
with mainline.
Thanks.
On Fri, May 16, 2008 at 8:14 PM, Robert Richter <[EMAIL PROTECTED]> wrote:
> Signed-off-by: Robert Richter <[EMAIL PROTECTED]>
> ---
> arch/x86/kernel/cpu/common.c | 1 -
> arch/x86/kernel/process_32.c | 2 +-
> arch/x86/kernel/smpboot_64.c | 1110
> --------------------------------------
> include/asm-x86/cpufeature_32.h | 177 ------
> include/asm-x86/thread_info_32.h | 7 +-
> include/asm-x86/thread_info_64.h | 2 +-
> 6 files changed, 6 insertions(+), 1293 deletions(-)
> delete mode 100644 arch/x86/kernel/smpboot_64.c
> delete mode 100644 include/asm-x86/cpufeature_32.h
>
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index cfc524d..316e6b1 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -6,7 +6,6 @@
> #include <linux/percpu.h>
> #include <linux/bootmem.h>
> #include <linux/perfmon_kern.h>
> -#include <asm/semaphore.h>
> #include <asm/processor.h>
> #include <asm/i387.h>
> #include <asm/msr.h>
> diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
> index 526378d..957c3bd 100644
> --- a/arch/x86/kernel/process_32.c
> +++ b/arch/x86/kernel/process_32.c
> @@ -527,7 +527,6 @@ __switch_to_xtra(struct task_struct *prev_p, struct
> task_struct *next_p,
> hard_enable_TSC();
> }
>
> -
> #ifdef X86_BTS
> if (test_tsk_thread_flag(prev_p, TIF_BTS_TRACE_TS))
> ptrace_bts_take_timestamp(prev_p, BTS_TASK_DEPARTS);
> @@ -536,6 +535,7 @@ __switch_to_xtra(struct task_struct *prev_p, struct
> task_struct *next_p,
> ptrace_bts_take_timestamp(next_p, BTS_TASK_ARRIVES);
> #endif
>
> +
> if (!test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
> /*
> * Disable the bitmap via an invalid offset. We still cache
> diff --git a/arch/x86/kernel/smpboot_64.c b/arch/x86/kernel/smpboot_64.c
> deleted file mode 100644
> index 1955c99..0000000
> --- a/arch/x86/kernel/smpboot_64.c
> +++ /dev/null
> @@ -1,1110 +0,0 @@
> -/*
> - * x86 SMP booting functions
> - *
> - * (c) 1995 Alan Cox, Building #3 <[EMAIL PROTECTED]>
> - * (c) 1998, 1999, 2000 Ingo Molnar <[EMAIL PROTECTED]>
> - * Copyright 2001 Andi Kleen, SuSE Labs.
> - *
> - * Much of the core SMP work is based on previous work by Thomas Radke,
> to
> - * whom a great many thanks are extended.
> - *
> - * Thanks to Intel for making available several different Pentium,
> - * Pentium Pro and Pentium-II/Xeon MP machines.
> - * Original development of Linux SMP code supported by Caldera.
> - *
> - * This code is released under the GNU General Public License version 2
> - *
> - * Fixes
> - * Felix Koop : NR_CPUS used properly
> - * Jose Renau : Handle single CPU case.
> - * Alan Cox : By repeated request 8) - Total
> BogoMIP report.
> - * Greg Wright : Fix for kernel stacks panic.
> - * Erich Boleyn : MP v1.4 and additional changes.
> - * Matthias Sattler : Changes for 2.1 kernel map.
> - * Michel Lespinasse : Changes for 2.1 kernel map.
> - * Michael Chastain : Change trampoline.S to gnu as.
> - * Alan Cox : Dumb bug: 'B' step PPro's are fine
> - * Ingo Molnar : Added APIC timers, based on code
> - * from Jose Renau
> - * Ingo Molnar : various cleanups and rewrites
> - * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP"
> bug.
> - * Maciej W. Rozycki : Bits for genuine 82489DX APICs
> - * Andi Kleen : Changed for SMP boot into long mode.
> - * Rusty Russell : Hacked into shape for new "hotplug"
> boot process.
> - * Andi Kleen : Converted to new state machine.
> - * Various cleanups.
> - * Probably mostly hotplug CPU ready now.
> - * Ashok Raj : CPU hotplug support
> - */
> -
> -
> -#include <linux/init.h>
> -
> -#include <linux/mm.h>
> -#include <linux/kernel_stat.h>
> -#include <linux/bootmem.h>
> -#include <linux/thread_info.h>
> -#include <linux/module.h>
> -#include <linux/delay.h>
> -#include <linux/mc146818rtc.h>
> -#include <linux/smp.h>
> -#include <linux/kdebug.h>
> -#include <linux/perfmon_kern.h>
> -
> -#include <asm/mtrr.h>
> -#include <asm/pgalloc.h>
> -#include <asm/desc.h>
> -#include <asm/tlbflush.h>
> -#include <asm/proto.h>
> -#include <asm/nmi.h>
> -#include <asm/irq.h>
> -#include <asm/hw_irq.h>
> -#include <asm/numa.h>
> -
> -/* Number of siblings per CPU package */
> -int smp_num_siblings = 1;
> -EXPORT_SYMBOL(smp_num_siblings);
> -
> -/* Last level cache ID of each logical CPU */
> -DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
> -
> -/* Bitmask of currently online CPUs */
> -cpumask_t cpu_online_map __read_mostly;
> -
> -EXPORT_SYMBOL(cpu_online_map);
> -
> -/*
> - * Private maps to synchronize booting between AP and BP.
> - * Probably not needed anymore, but it makes for easier debugging. -AK
> - */
> -cpumask_t cpu_callin_map;
> -cpumask_t cpu_callout_map;
> -cpumask_t cpu_possible_map;
> -EXPORT_SYMBOL(cpu_possible_map);
> -
> -/* Per CPU bogomips and other parameters */
> -DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
> -EXPORT_PER_CPU_SYMBOL(cpu_info);
> -
> -/* Set when the idlers are all forked */
> -int smp_threads_ready;
> -
> -/* representing HT siblings of each logical CPU */
> -DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
> -EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
> -
> -/* representing HT and core siblings of each logical CPU */
> -DEFINE_PER_CPU(cpumask_t, cpu_core_map);
> -EXPORT_PER_CPU_SYMBOL(cpu_core_map);
> -
> -/*
> - * Trampoline 80x86 program as an array.
> - */
> -
> -extern const unsigned char trampoline_data[];
> -extern const unsigned char trampoline_end[];
> -
> -/* State of each CPU */
> -DEFINE_PER_CPU(int, cpu_state) = { 0 };
> -
> -/*
> - * Store all idle threads, this can be reused instead of creating
> - * a new thread. Also avoids complicated thread destroy functionality
> - * for idle threads.
> - */
> -#ifdef CONFIG_HOTPLUG_CPU
> -/*
> - * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
> - * removed after init for !CONFIG_HOTPLUG_CPU.
> - */
> -static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
> -#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
> -#define set_idle_for_cpu(x,p) (per_cpu(idle_thread_array, x) = (p))
> -#else
> -struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
> -#define get_idle_for_cpu(x) (idle_thread_array[(x)])
> -#define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p))
> -#endif
> -
> -
> -/*
> - * Currently trivial. Write the real->protected mode
> - * bootstrap into the page concerned. The caller
> - * has made sure it's suitably aligned.
> - */
> -
> -static unsigned long __cpuinit setup_trampoline(void)
> -{
> - void *tramp = __va(SMP_TRAMPOLINE_BASE);
> - memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
> - return virt_to_phys(tramp);
> -}
> -
> -/*
> - * The bootstrap kernel entry code has set these up. Save them for
> - * a given CPU
> - */
> -
> -static void __cpuinit smp_store_cpu_info(int id)
> -{
> - struct cpuinfo_x86 *c = &cpu_data(id);
> -
> - *c = boot_cpu_data;
> - c->cpu_index = id;
> - identify_cpu(c);
> - print_cpu_info(c);
> -}
> -
> -static atomic_t init_deasserted __cpuinitdata;
> -
> -/*
> - * Report back to the Boot Processor.
> - * Running on AP.
> - */
> -void __cpuinit smp_callin(void)
> -{
> - int cpuid, phys_id;
> - unsigned long timeout;
> -
> - /*
> - * If waken up by an INIT in an 82489DX configuration
> - * we may get here before an INIT-deassert IPI reaches
> - * our local APIC. We have to wait for the IPI or we'll
> - * lock up on an APIC access.
> - */
> - while (!atomic_read(&init_deasserted))
> - cpu_relax();
> -
> - /*
> - * (This works even if the APIC is not enabled.)
> - */
> - phys_id = GET_APIC_ID(apic_read(APIC_ID));
> - cpuid = smp_processor_id();
> - if (cpu_isset(cpuid, cpu_callin_map)) {
> - panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
> - phys_id, cpuid);
> - }
> - Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
> -
> - /*
> - * STARTUP IPIs are fragile beasts as they might sometimes
> - * trigger some glue motherboard logic. Complete APIC bus
> - * silence for 1 second, this overestimates the time the
> - * boot CPU is spending to send the up to 2 STARTUP IPIs
> - * by a factor of two. This should be enough.
> - */
> -
> - /*
> - * Waiting 2s total for startup (udelay is not yet working)
> - */
> - timeout = jiffies + 2*HZ;
> - while (time_before(jiffies, timeout)) {
> - /*
> - * Has the boot CPU finished it's STARTUP sequence?
> - */
> - if (cpu_isset(cpuid, cpu_callout_map))
> - break;
> - cpu_relax();
> - }
> -
> - if (!time_before(jiffies, timeout)) {
> - panic("smp_callin: CPU%d started up but did not get a
> callout!\n",
> - cpuid);
> - }
> -
> - /*
> - * the boot CPU has finished the init stage and is spinning
> - * on callin_map until we finish. We are free to set up this
> - * CPU, first the APIC. (this is probably redundant on most
> - * boards)
> - */
> -
> - Dprintk("CALLIN, before setup_local_APIC().\n");
> - setup_local_APIC();
> - end_local_APIC_setup();
> -
> - /*
> - * Get our bogomips.
> - *
> - * Need to enable IRQs because it can take longer and then
> - * the NMI watchdog might kill us.
> - */
> - local_irq_enable();
> - calibrate_delay();
> - local_irq_disable();
> - Dprintk("Stack at about %p\n",&cpuid);
> -
> - /*
> - * Save our processor parameters
> - */
> - smp_store_cpu_info(cpuid);
> -
> - /*
> - * Allow the master to continue.
> - */
> - cpu_set(cpuid, cpu_callin_map);
> -}
> -
> -/* maps the cpu to the sched domain representing multi-core */
> -cpumask_t cpu_coregroup_map(int cpu)
> -{
> - struct cpuinfo_x86 *c = &cpu_data(cpu);
> - /*
> - * For perf, we return last level cache shared map.
> - * And for power savings, we return cpu_core_map
> - */
> - if (sched_mc_power_savings || sched_smt_power_savings)
> - return per_cpu(cpu_core_map, cpu);
> - else
> - return c->llc_shared_map;
> -}
> -
> -/* representing cpus for which sibling maps can be computed */
> -static cpumask_t cpu_sibling_setup_map;
> -
> -static inline void set_cpu_sibling_map(int cpu)
> -{
> - int i;
> - struct cpuinfo_x86 *c = &cpu_data(cpu);
> -
> - cpu_set(cpu, cpu_sibling_setup_map);
> -
> - if (smp_num_siblings > 1) {
> - for_each_cpu_mask(i, cpu_sibling_setup_map) {
> - if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
> - c->cpu_core_id == cpu_data(i).cpu_core_id) {
> - cpu_set(i, per_cpu(cpu_sibling_map, cpu));
> - cpu_set(cpu, per_cpu(cpu_sibling_map, i));
> - cpu_set(i, per_cpu(cpu_core_map, cpu));
> - cpu_set(cpu, per_cpu(cpu_core_map, i));
> - cpu_set(i, c->llc_shared_map);
> - cpu_set(cpu, cpu_data(i).llc_shared_map);
> - }
> - }
> - } else {
> - cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
> - }
> -
> - cpu_set(cpu, c->llc_shared_map);
> -
> - if (current_cpu_data.x86_max_cores == 1) {
> - per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
> - c->booted_cores = 1;
> - return;
> - }
> -
> - for_each_cpu_mask(i, cpu_sibling_setup_map) {
> - if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
> - per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
> - cpu_set(i, c->llc_shared_map);
> - cpu_set(cpu, cpu_data(i).llc_shared_map);
> - }
> - if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
> - cpu_set(i, per_cpu(cpu_core_map, cpu));
> - cpu_set(cpu, per_cpu(cpu_core_map, i));
> - /*
> - * Does this new cpu bringup a new core?
> - */
> - if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
> - /*
> - * for each core in package, increment
> - * the booted_cores for this new cpu
> - */
> - if (first_cpu(per_cpu(cpu_sibling_map, i)) ==
> i)
> - c->booted_cores++;
> - /*
> - * increment the core count for all
> - * the other cpus in this package
> - */
> - if (i != cpu)
> - cpu_data(i).booted_cores++;
> - } else if (i != cpu && !c->booted_cores)
> - c->booted_cores = cpu_data(i).booted_cores;
> - }
> - }
> -}
> -
> -/*
> - * Setup code on secondary processor (after comming out of the trampoline)
> - */
> -void __cpuinit start_secondary(void)
> -{
> - /*
> - * Dont put anything before smp_callin(), SMP
> - * booting is too fragile that we want to limit the
> - * things done here to the most necessary things.
> - */
> - cpu_init();
> - preempt_disable();
> - smp_callin();
> -
> - /* otherwise gcc will move up the smp_processor_id before the
> cpu_init */
> - barrier();
> -
> - /*
> - * Check TSC sync first:
> - */
> - check_tsc_sync_target();
> -
> - if (nmi_watchdog == NMI_IO_APIC) {
> - disable_8259A_irq(0);
> - enable_NMI_through_LVT0();
> - enable_8259A_irq(0);
> - }
> -
> - /*
> - * The sibling maps must be set before turing the online map on for
> - * this cpu
> - */
> - set_cpu_sibling_map(smp_processor_id());
> -
> - /*
> - * We need to hold call_lock, so there is no inconsistency
> - * between the time smp_call_function() determines number of
> - * IPI recipients, and the time when the determination is made
> - * for which cpus receive the IPI in genapic_flat.c. Holding this
> - * lock helps us to not include this cpu in a currently in progress
> - * smp_call_function().
> - */
> - lock_ipi_call_lock();
> - spin_lock(&vector_lock);
> -
> - /* Setup the per cpu irq handling data structures */
> - __setup_vector_irq(smp_processor_id());
> - /*
> - * Allow the master to continue.
> - */
> - cpu_set(smp_processor_id(), cpu_online_map);
> - per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
> - spin_unlock(&vector_lock);
> -
> - unlock_ipi_call_lock();
> -
> - setup_secondary_clock();
> -
> - cpu_idle();
> -}
> -
> -extern volatile unsigned long init_rsp;
> -extern void (*initial_code)(void);
> -
> -#ifdef APIC_DEBUG
> -static void inquire_remote_apic(int apicid)
> -{
> - unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
> - char *names[] = { "ID", "VERSION", "SPIV" };
> - int timeout;
> - u32 status;
> -
> - printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
> -
> - for (i = 0; i < ARRAY_SIZE(regs); i++) {
> - printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
> -
> - /*
> - * Wait for idle.
> - */
> - status = safe_apic_wait_icr_idle();
> - if (status)
> - printk(KERN_CONT
> - "a previous APIC delivery may have failed\n");
> -
> - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
> - apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]);
> -
> - timeout = 0;
> - do {
> - udelay(100);
> - status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
> - } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
> -
> - switch (status) {
> - case APIC_ICR_RR_VALID:
> - status = apic_read(APIC_RRR);
> - printk(KERN_CONT "%08x\n", status);
> - break;
> - default:
> - printk(KERN_CONT "failed\n");
> - }
> - }
> -}
> -#endif
> -
> -/*
> - * Kick the secondary to wake up.
> - */
> -static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int
> start_rip)
> -{
> - unsigned long send_status, accept_status = 0;
> - int maxlvt, num_starts, j;
> -
> - Dprintk("Asserting INIT.\n");
> -
> - /*
> - * Turn INIT on target chip
> - */
> - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
> -
> - /*
> - * Send IPI
> - */
> - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
> - | APIC_DM_INIT);
> -
> - Dprintk("Waiting for send to finish...\n");
> - send_status = safe_apic_wait_icr_idle();
> -
> - mdelay(10);
> -
> - Dprintk("Deasserting INIT.\n");
> -
> - /* Target chip */
> - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
> -
> - /* Send IPI */
> - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
> -
> - Dprintk("Waiting for send to finish...\n");
> - send_status = safe_apic_wait_icr_idle();
> -
> - mb();
> - atomic_set(&init_deasserted, 1);
> -
> - num_starts = 2;
> -
> - /*
> - * Run STARTUP IPI loop.
> - */
> - Dprintk("#startup loops: %d.\n", num_starts);
> -
> - maxlvt = lapic_get_maxlvt();
> -
> - for (j = 1; j <= num_starts; j++) {
> - Dprintk("Sending STARTUP #%d.\n",j);
> - apic_write(APIC_ESR, 0);
> - apic_read(APIC_ESR);
> - Dprintk("After apic_write.\n");
> -
> - /*
> - * STARTUP IPI
> - */
> -
> - /* Target chip */
> - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
> -
> - /* Boot on the stack */
> - /* Kick the second */
> - apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12));
> -
> - /*
> - * Give the other CPU some time to accept the IPI.
> - */
> - udelay(300);
> -
> - Dprintk("Startup point 1.\n");
> -
> - Dprintk("Waiting for send to finish...\n");
> - send_status = safe_apic_wait_icr_idle();
> -
> - /*
> - * Give the other CPU some time to accept the IPI.
> - */
> - udelay(200);
> - /*
> - * Due to the Pentium erratum 3AP.
> - */
> - if (maxlvt > 3) {
> - apic_write(APIC_ESR, 0);
> - }
> - accept_status = (apic_read(APIC_ESR) & 0xEF);
> - if (send_status || accept_status)
> - break;
> - }
> - Dprintk("After Startup.\n");
> -
> - if (send_status)
> - printk(KERN_ERR "APIC never delivered???\n");
> - if (accept_status)
> - printk(KERN_ERR "APIC delivery error (%lx).\n",
> accept_status);
> -
> - return (send_status | accept_status);
> -}
> -
> -struct create_idle {
> - struct work_struct work;
> - struct task_struct *idle;
> - struct completion done;
> - int cpu;
> -};
> -
> -static void __cpuinit do_fork_idle(struct work_struct *work)
> -{
> - struct create_idle *c_idle =
> - container_of(work, struct create_idle, work);
> -
> - c_idle->idle = fork_idle(c_idle->cpu);
> - complete(&c_idle->done);
> -}
> -
> -/*
> - * Boot one CPU.
> - */
> -static int __cpuinit do_boot_cpu(int cpu, int apicid)
> -{
> - unsigned long boot_error;
> - int timeout;
> - unsigned long start_rip;
> - struct create_idle c_idle = {
> - .cpu = cpu,
> - .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
> - };
> - INIT_WORK(&c_idle.work, do_fork_idle);
> -
> - /* allocate memory for gdts of secondary cpus. Hotplug is considered
> */
> - if (!cpu_gdt_descr[cpu].address &&
> - !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
> - printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
> - return -1;
> - }
> -
> - /* Allocate node local memory for AP pdas */
> - if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
> - struct x8664_pda *newpda, *pda;
> - int node = cpu_to_node(cpu);
> - pda = cpu_pda(cpu);
> - newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC,
> - node);
> - if (newpda) {
> - memcpy(newpda, pda, sizeof (struct x8664_pda));
> - cpu_pda(cpu) = newpda;
> - } else
> - printk(KERN_ERR
> - "Could not allocate node local PDA for CPU %d on node %d\n",
> - cpu, node);
> - }
> -
> - alternatives_smp_switch(1);
> -
> - c_idle.idle = get_idle_for_cpu(cpu);
> -
> - if (c_idle.idle) {
> - c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
> - (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
> - init_idle(c_idle.idle, cpu);
> - goto do_rest;
> - }
> -
> - /*
> - * During cold boot process, keventd thread is not spun up yet.
> - * When we do cpu hot-add, we create idle threads on the fly, we
> should
> - * not acquire any attributes from the calling context. Hence the
> clean
> - * way to create kernel_threads() is to do that from keventd().
> - * We do the current_is_keventd() due to the fact that ACPI notifier
> - * was also queuing to keventd() and when the caller is already
> running
> - * in context of keventd(), we would end up with locking up the
> keventd
> - * thread.
> - */
> - if (!keventd_up() || current_is_keventd())
> - c_idle.work.func(&c_idle.work);
> - else {
> - schedule_work(&c_idle.work);
> - wait_for_completion(&c_idle.done);
> - }
> -
> - if (IS_ERR(c_idle.idle)) {
> - printk("failed fork for CPU %d\n", cpu);
> - return PTR_ERR(c_idle.idle);
> - }
> -
> - set_idle_for_cpu(cpu, c_idle.idle);
> -
> -do_rest:
> -
> - cpu_pda(cpu)->pcurrent = c_idle.idle;
> -
> - start_rip = setup_trampoline();
> -
> - init_rsp = c_idle.idle->thread.sp;
> - load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
> - initial_code = start_secondary;
> - clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
> -
> - printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu,
> - cpus_weight(cpu_present_map),
> - apicid);
> -
> - /*
> - * This grunge runs the startup process for
> - * the targeted processor.
> - */
> -
> - atomic_set(&init_deasserted, 0);
> -
> - Dprintk("Setting warm reset code and vector.\n");
> -
> - CMOS_WRITE(0xa, 0xf);
> - local_flush_tlb();
> - Dprintk("1.\n");
> - *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
> - Dprintk("2.\n");
> - *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
> - Dprintk("3.\n");
> -
> - /*
> - * Be paranoid about clearing APIC errors.
> - */
> - apic_write(APIC_ESR, 0);
> - apic_read(APIC_ESR);
> -
> - /*
> - * Status is now clean
> - */
> - boot_error = 0;
> -
> - /*
> - * Starting actual IPI sequence...
> - */
> - boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
> -
> - if (!boot_error) {
> - /*
> - * allow APs to start initializing.
> - */
> - Dprintk("Before Callout %d.\n", cpu);
> - cpu_set(cpu, cpu_callout_map);
> - Dprintk("After Callout %d.\n", cpu);
> -
> - /*
> - * Wait 5s total for a response
> - */
> - for (timeout = 0; timeout < 50000; timeout++) {
> - if (cpu_isset(cpu, cpu_callin_map))
> - break; /* It has booted */
> - udelay(100);
> - }
> -
> - if (cpu_isset(cpu, cpu_callin_map)) {
> - /* number CPUs logically, starting from 1 (BSP is 0)
> */
> - Dprintk("CPU has booted.\n");
> - } else {
> - boot_error = 1;
> - if (*((volatile unsigned char
> *)phys_to_virt(SMP_TRAMPOLINE_BASE))
> - == 0xA5)
> - /* trampoline started but...? */
> - printk("Stuck ??\n");
> - else
> - /* trampoline code not run */
> - printk("Not responding.\n");
> -#ifdef APIC_DEBUG
> - inquire_remote_apic(apicid);
> -#endif
> - }
> - }
> - if (boot_error) {
> - cpu_clear(cpu, cpu_callout_map); /* was set here
> (do_boot_cpu()) */
> - clear_bit(cpu, (unsigned long *)&cpu_initialized); /* was set
> by cpu_init() */
> - clear_node_cpumask(cpu); /* was set by numa_add_cpu */
> - cpu_clear(cpu, cpu_present_map);
> - cpu_clear(cpu, cpu_possible_map);
> - per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -cycles_t cacheflush_time;
> -unsigned long cache_decay_ticks;
> -
> -/*
> - * Cleanup possible dangling ends...
> - */
> -static __cpuinit void smp_cleanup_boot(void)
> -{
> - /*
> - * Paranoid: Set warm reset code and vector here back
> - * to default values.
> - */
> - CMOS_WRITE(0, 0xf);
> -
> - /*
> - * Reset trampoline flag
> - */
> - *((volatile int *) phys_to_virt(0x467)) = 0;
> -}
> -
> -/*
> - * Fall back to non SMP mode after errors.
> - *
> - * RED-PEN audit/test this more. I bet there is more state messed up here.
> - */
> -static __init void disable_smp(void)
> -{
> - cpu_present_map = cpumask_of_cpu(0);
> - cpu_possible_map = cpumask_of_cpu(0);
> - if (smp_found_config)
> - phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
> - else
> - phys_cpu_present_map = physid_mask_of_physid(0);
> - cpu_set(0, per_cpu(cpu_sibling_map, 0));
> - cpu_set(0, per_cpu(cpu_core_map, 0));
> -}
> -
> -#ifdef CONFIG_HOTPLUG_CPU
> -
> -int additional_cpus __initdata = -1;
> -
> -/*
> - * cpu_possible_map should be static, it cannot change as cpu's
> - * are onlined, or offlined. The reason is per-cpu data-structures
> - * are allocated by some modules at init time, and dont expect to
> - * do this dynamically on cpu arrival/departure.
> - * cpu_present_map on the other hand can change dynamically.
> - * In case when cpu_hotplug is not compiled, then we resort to current
> - * behaviour, which is cpu_possible == cpu_present.
> - * - Ashok Raj
> - *
> - * Three ways to find out the number of additional hotplug CPUs:
> - * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
> - * - The user can overwrite it with additional_cpus=NUM
> - * - Otherwise don't reserve additional CPUs.
> - * We do this because additional CPUs waste a lot of memory.
> - * -AK
> - */
> -__init void prefill_possible_map(void)
> -{
> - int i;
> - int possible;
> -
> - if (additional_cpus == -1) {
> - if (disabled_cpus > 0)
> - additional_cpus = disabled_cpus;
> - else
> - additional_cpus = 0;
> - }
> - possible = num_processors + additional_cpus;
> - if (possible > NR_CPUS)
> - possible = NR_CPUS;
> -
> - printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
> - possible,
> - max_t(int, possible - num_processors, 0));
> -
> - for (i = 0; i < possible; i++)
> - cpu_set(i, cpu_possible_map);
> -}
> -#endif
> -
> -/*
> - * Various sanity checks.
> - */
> -static int __init smp_sanity_check(unsigned max_cpus)
> -{
> - if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
> - printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
> - hard_smp_processor_id());
> - physid_set(hard_smp_processor_id(), phys_cpu_present_map);
> - }
> -
> - /*
> - * If we couldn't find an SMP configuration at boot time,
> - * get out of here now!
> - */
> - if (!smp_found_config) {
> - printk(KERN_NOTICE "SMP motherboard not detected.\n");
> - disable_smp();
> - if (APIC_init_uniprocessor())
> - printk(KERN_NOTICE "Local APIC not detected."
> - " Using dummy APIC emulation.\n");
> - return -1;
> - }
> -
> - /*
> - * Should not be necessary because the MP table should list the boot
> - * CPU too, but we do it for the sake of robustness anyway.
> - */
> - if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
> - printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the
> BIOS.\n",
> - boot_cpu_id);
> - physid_set(hard_smp_processor_id(), phys_cpu_present_map);
> - }
> -
> - /*
> - * If we couldn't find a local APIC, then get out of here now!
> - */
> - if (!cpu_has_apic) {
> - printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
> - boot_cpu_id);
> - printk(KERN_ERR "... forcing use of dummy APIC emulation.
> (tell your hw vendor)\n");
> - nr_ioapics = 0;
> - return -1;
> - }
> -
> - /*
> - * If SMP should be disabled, then really disable it!
> - */
> - if (!max_cpus) {
> - printk(KERN_INFO "SMP mode deactivated, forcing use of dummy
> APIC emulation.\n");
> - nr_ioapics = 0;
> - return -1;
> - }
> -
> - return 0;
> -}
> -
> -static void __init smp_cpu_index_default(void)
> -{
> - int i;
> - struct cpuinfo_x86 *c;
> -
> - for_each_cpu_mask(i, cpu_possible_map) {
> - c = &cpu_data(i);
> - /* mark all to hotplug */
> - c->cpu_index = NR_CPUS;
> - }
> -}
> -
> -/*
> - * Prepare for SMP bootup. The MP table or ACPI has been read
> - * earlier. Just do some sanity checking here and enable APIC mode.
> - */
> -void __init smp_prepare_cpus(unsigned int max_cpus)
> -{
> - nmi_watchdog_default();
> - smp_cpu_index_default();
> - current_cpu_data = boot_cpu_data;
> - current_thread_info()->cpu = 0; /* needed? */
> - set_cpu_sibling_map(0);
> -
> - if (smp_sanity_check(max_cpus) < 0) {
> - printk(KERN_INFO "SMP disabled\n");
> - disable_smp();
> - return;
> - }
> -
> -
> - /*
> - * Switch from PIC to APIC mode.
> - */
> - setup_local_APIC();
> -
> - /*
> - * Enable IO APIC before setting up error vector
> - */
> - if (!skip_ioapic_setup && nr_ioapics)
> - enable_IO_APIC();
> - end_local_APIC_setup();
> -
> - if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) {
> - panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
> - GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id);
> - /* Or can we switch back to PIC here? */
> - }
> -
> - /*
> - * Now start the IO-APICs
> - */
> - if (!skip_ioapic_setup && nr_ioapics)
> - setup_IO_APIC();
> - else
> - nr_ioapics = 0;
> -
> - /*
> - * Set up local APIC timer on boot CPU.
> - */
> -
> - setup_boot_clock();
> -}
> -
> -/*
> - * Early setup to make printk work.
> - */
> -void __init smp_prepare_boot_cpu(void)
> -{
> - int me = smp_processor_id();
> - /* already set me in cpu_online_map in boot_cpu_init() */
> - cpu_set(me, cpu_callout_map);
> - per_cpu(cpu_state, me) = CPU_ONLINE;
> -}
> -
> -/*
> - * Entry point to boot a CPU.
> - */
> -int __cpuinit __cpu_up(unsigned int cpu)
> -{
> - int apicid = cpu_present_to_apicid(cpu);
> - unsigned long flags;
> - int err;
> -
> - WARN_ON(irqs_disabled());
> -
> - Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
> -
> - if (apicid == BAD_APICID || apicid == boot_cpu_id ||
> - !physid_isset(apicid, phys_cpu_present_map)) {
> - printk("__cpu_up: bad cpu %d\n", cpu);
> - return -EINVAL;
> - }
> -
> - /*
> - * Already booted CPU?
> - */
> - if (cpu_isset(cpu, cpu_callin_map)) {
> - Dprintk("do_boot_cpu %d Already started\n", cpu);
> - return -ENOSYS;
> - }
> -
> - /*
> - * Save current MTRR state in case it was changed since early boot
> - * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
> - */
> - mtrr_save_state();
> -
> - per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
> - /* Boot it! */
> - err = do_boot_cpu(cpu, apicid);
> - if (err < 0) {
> - Dprintk("do_boot_cpu failed %d\n", err);
> - return err;
> - }
> -
> - /* Unleash the CPU! */
> - Dprintk("waiting for cpu %d\n", cpu);
> -
> - /*
> - * Make sure and check TSC sync:
> - */
> - local_irq_save(flags);
> - check_tsc_sync_source(cpu);
> - local_irq_restore(flags);
> -
> - while (!cpu_isset(cpu, cpu_online_map))
> - cpu_relax();
> - err = 0;
> -
> - return err;
> -}
> -
> -/*
> - * Finish the SMP boot.
> - */
> -void __init smp_cpus_done(unsigned int max_cpus)
> -{
> - smp_cleanup_boot();
> - setup_ioapic_dest();
> - check_nmi_watchdog();
> -}
> -
> -#ifdef CONFIG_HOTPLUG_CPU
> -
> -static void remove_siblinginfo(int cpu)
> -{
> - int sibling;
> - struct cpuinfo_x86 *c = &cpu_data(cpu);
> -
> - for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
> - cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
> - /*
> - * last thread sibling in this cpu core going down
> - */
> - if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
> - cpu_data(sibling).booted_cores--;
> - }
> -
> - for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
> - cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
> - cpus_clear(per_cpu(cpu_sibling_map, cpu));
> - cpus_clear(per_cpu(cpu_core_map, cpu));
> - c->phys_proc_id = 0;
> - c->cpu_core_id = 0;
> - cpu_clear(cpu, cpu_sibling_setup_map);
> -}
> -
> -static void __ref remove_cpu_from_maps(void)
> -{
> - int cpu = smp_processor_id();
> -
> - cpu_clear(cpu, cpu_callout_map);
> - cpu_clear(cpu, cpu_callin_map);
> - clear_bit(cpu, (unsigned long *)&cpu_initialized); /* was set by
> cpu_init() */
> - clear_node_cpumask(cpu);
> -}
> -
> -int __cpu_disable(void)
> -{
> - int cpu = smp_processor_id();
> -
> - /*
> - * Perhaps use cpufreq to drop frequency, but that could go
> - * into generic code.
> - *
> - * We won't take down the boot processor on i386 due to some
> - * interrupts only being able to be serviced by the BSP.
> - * Especially so if we're not using an IOAPIC -zwane
> - */
> - if (cpu == 0)
> - return -EBUSY;
> -
> - if (nmi_watchdog == NMI_LOCAL_APIC)
> - stop_apic_nmi_watchdog(NULL);
> - clear_local_APIC();
> -
> - /*
> - * HACK:
> - * Allow any queued timer interrupts to get serviced
> - * This is only a temporary solution until we cleanup
> - * fixup_irqs as we do for IA64.
> - */
> - local_irq_enable();
> - mdelay(1);
> -
> - local_irq_disable();
> - remove_siblinginfo(cpu);
> -
> - spin_lock(&vector_lock);
> - /* It's now safe to remove this processor from the online map */
> - cpu_clear(cpu, cpu_online_map);
> - spin_unlock(&vector_lock);
> - remove_cpu_from_maps();
> - fixup_irqs(cpu_online_map);
> - pfm_cpu_disable();
> - return 0;
> -}
> -
> -void __cpu_die(unsigned int cpu)
> -{
> - /* We don't do anything here: idle task is faking death itself. */
> - unsigned int i;
> -
> - for (i = 0; i < 10; i++) {
> - /* They ack this in play_dead by setting CPU_DEAD */
> - if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
> - printk ("CPU %d is now offline\n", cpu);
> - if (1 == num_online_cpus())
> - alternatives_smp_switch(0);
> - return;
> - }
> - msleep(100);
> - }
> - printk(KERN_ERR "CPU %u didn't die...\n", cpu);
> -}
> -
> -static __init int setup_additional_cpus(char *s)
> -{
> - return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
> -}
> -early_param("additional_cpus", setup_additional_cpus);
> -
> -#else /* ... !CONFIG_HOTPLUG_CPU */
> -
> -int __cpu_disable(void)
> -{
> - return -ENOSYS;
> -}
> -
> -void __cpu_die(unsigned int cpu)
> -{
> - /* We said "no" in __cpu_disable */
> - BUG();
> -}
> -#endif /* CONFIG_HOTPLUG_CPU */
> diff --git a/include/asm-x86/cpufeature_32.h b/include/asm-x86/cpufeature_32.h
> deleted file mode 100644
> index 96378f8..0000000
> --- a/include/asm-x86/cpufeature_32.h
> +++ /dev/null
> @@ -1,177 +0,0 @@
> -/*
> - * cpufeature.h
> - *
> - * Defines x86 CPU feature bits
> - */
> -
> -#ifndef __ASM_I386_CPUFEATURE_H
> -#define __ASM_I386_CPUFEATURE_H
> -
> -#ifndef __ASSEMBLY__
> -#include <linux/bitops.h>
> -#endif
> -#include <asm/required-features.h>
> -
> -#define NCAPINTS 8 /* N 32-bit words worth of info */
> -
> -/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
> -#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
> -#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions
> */
> -#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
> -#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
> -#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
> -#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific
> Registers, RDMSR, WRMSR */
> -#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address
> Extensions */
> -#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check
> Architecture */
> -#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
> -#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
> -#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
> -#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
> -#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
> -#define X86_FEATURE_MCA (0*32+14) /* Machine Check
> Architecture */
> -#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and
> FCOMI too if FPU present) */
> -#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
> -#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
> -#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
> -#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction
> */
> -#define X86_FEATURE_DS (0*32+21) /* Debug Store */
> -#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
> -#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
> -#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions
> (fast save and restore */
> - /* of FPU context), and CR4.OSFXSR
> available */
> -#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD
> Extensions */
> -#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
> -#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
> -#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
> -#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control
> */
> -#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
> -
> -/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
> -/* Don't duplicate feature flags which are redundant with Intel! */
> -#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
> -#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
> -#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
> -#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
> -#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
> -#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
> -#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
> -#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
> -
> -/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
> -#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
> -#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
> -#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
> -
> -/* Other features, Linux-defined mapping, word 3 */
> -/* This range is used for feature bits which conflict or are synthesized */
> -#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
> -#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
> -#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
> -#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
> -/* cpu types for specific tunings: */
> -#define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
> -#define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
> -#define X86_FEATURE_P3 (3*32+ 6) /* P3 */
> -#define X86_FEATURE_P4 (3*32+ 7) /* P4 */
> -#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
> -#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
> -#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
> -#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
> -#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
> -#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
> -/* 14 free */
> -#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
> -#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this
> CPU */
> -
> -/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
> -#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
> -#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
> -#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
> -#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
> -#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
> -#define X86_FEATURE_CID (4*32+10) /* Context ID */
> -#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
> -#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
> -#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
> -
> -/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
> -#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn)
> */
> -#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
> -#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
> -#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
> -#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2
> */
> -#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
> -#define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
> -#define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
> -#define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery
> Multiplier */
> -#define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
> -
> -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
> -#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
> -#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid
> */
> -
> -/*
> - * Auxiliary flags: Linux defined - For features scattered in various
> - * CPUID levels like 0x6, 0xA etc
> - */
> -#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic
> Acceleration */
> -
> -#define cpu_has(c, bit)
> \
> - (__builtin_constant_p(bit) && \
> - ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
> - (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \
> - (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \
> - (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \
> - (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
> - (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
> - (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
> - (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \
> - ? 1 : \
> - test_bit(bit, (c)->x86_capability))
> -#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
> -
> -#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
> -#define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
> -#define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
> -#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
> -#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
> -#define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
> -#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
> -#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
> -#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
> -#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
> -#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
> -#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
> -#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
> -#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
> -#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
> -#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
> -#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
> -#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
> -#define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
> -#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
> -#define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
> -#define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
> -#define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
> -#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
> -#define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
> -#define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
> -#define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
> -#define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
> -#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
> -#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
> -#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
> -#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
> -#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
> -#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
> -#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
> -#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
> -
> -#endif /* __ASM_I386_CPUFEATURE_H */
> -
> -/*
> - * Local Variables:
> - * mode:c
> - * comment-column:42
> - * End:
> - */
> diff --git a/include/asm-x86/thread_info_32.h
> b/include/asm-x86/thread_info_32.h
> index 4709b12..9a0e784 100644
> --- a/include/asm-x86/thread_info_32.h
> +++ b/include/asm-x86/thread_info_32.h
> @@ -172,12 +172,13 @@ static inline struct thread_info
> *current_thread_info(void)
> #define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP)
>
> /* flags to check in __switch_to() */
> -#define _TIF_WORK_CTXSW \
> - (_TIF_IO_BITMAP | _TIF_NOTSC | _TIF_DEBUGCTLMSR | \
> - _TIF_DS_AREA_MSR | _TIF_BTS_TRACE_TS | _TIF_PERFMON_CTXSW)
> +#define _TIF_WORK_CTXSW \
> + (_TIF_IO_BITMAP | _TIF_NOTSC | _TIF_DEBUGCTLMSR | \
> + _TIF_DS_AREA_MSR | _TIF_BTS_TRACE_TS | _TIF_PERFMON_CTXSW)
> #define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW
> #define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW | _TIF_DEBUG)
>
> +
> /*
> * Thread-synchronous status.
> *
> diff --git a/include/asm-x86/thread_info_64.h
> b/include/asm-x86/thread_info_64.h
> index 4056ee5..4d4832f 100644
> --- a/include/asm-x86/thread_info_64.h
> +++ b/include/asm-x86/thread_info_64.h
> @@ -157,7 +157,7 @@ static inline struct thread_info *stack_thread_info(void)
> /* work to do on any return to user space */
> #define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP)
>
> -#define _TIF_DO_NOTIFY_MASK \
> +#define _TIF_DO_NOTIFY_MASK \
> (_TIF_SIGPENDING|_TIF_SINGLESTEP|_TIF_MCE_NOTIFY|_TIF_HRTICK_RESCHED|\
> _TIF_PERFMON_WORK)
>
> --
> 1.5.3.7
>
>
>
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