Carl,

Patch applied.
Thanks.

On Fri, Jun 13, 2008 at 5:14 PM, Carl Love <[EMAIL PROTECTED]> wrote:
>
> The following patch sets the HW interrupt enable bits for the four
> 32 bit counters CELL currently supports.  This is needed to enable
> the virtual 64bit counters support by default.
>
> Signed-off-by: Carl Love <[EMAIL PROTECTED]>
>
> Index: linux-2.6.25.ppc64/arch/powerpc/perfmon/perfmon_cell.c
> ===================================================================
> --- linux-2.6.25.ppc64.orig/arch/powerpc/perfmon/perfmon_cell.c
> +++ linux-2.6.25.ppc64/arch/powerpc/perfmon/perfmon_cell.c
> @@ -91,7 +91,11 @@ static struct pfm_regmap_desc pfm_cell_p
>        PMC_D(PFM_REG_I, "trace_address",     0, 0, 0, 0),
>        PMC_D(PFM_REG_I, "ext_trace_timer",   0, 0, 0, 0),
>        PMC_D(PFM_REG_I, "pm_status",         0, 0, 0, 0),
> -       PMC_D(PFM_REG_I, "pm_control",        0, 0, 0, 0),
> +       /* set the interrupt overflow bit for the four 32 bit counters
> +        * that is currently supported.  Will need to fix when 32 and 16
> +        * bit counters are supported.
> +        */
> +       PMC_D(PFM_REG_I, "pm_control",        0xF0000000, 0xF0000000, 0, 0),
>        PMC_D(PFM_REG_I, "pm_interval",       0, 0, 0, 0), /* FIX: Does
> user-space also need read access to this one? */
>        PMC_D(PFM_REG_I, "pm_start_stop",     0, 0, 0, 0),
>  };
>
>
>
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