Robert,
Patch applied,
Thanks.
On Thu, Jun 19, 2008 at 4:04 PM, Robert Richter <[EMAIL PROTECTED]> wrote:
> This patch removes the workaround to access the Extended Config Space
> that is needed to setup IBS interrupts. PCI functions are replaced by
> standard PCI functions that support now ECS access.
>
> Signed-off-by: Robert Richter <[EMAIL PROTECTED]>
> ---
> arch/x86/pci/common.c | 1 -
> arch/x86/perfmon/perfmon_amd64.c | 100 +------------------------------------
> 2 files changed, 3 insertions(+), 98 deletions(-)
>
> diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
> index 3e11f47..940185e 100644
> --- a/arch/x86/pci/common.c
> +++ b/arch/x86/pci/common.c
> @@ -76,7 +76,6 @@ int pcibios_scanned;
> * configuration space.
> */
> DEFINE_SPINLOCK(pci_config_lock);
> -EXPORT_SYMBOL(pci_config_lock);
>
> static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d)
> {
> diff --git a/arch/x86/perfmon/perfmon_amd64.c
> b/arch/x86/perfmon/perfmon_amd64.c
> index 20bafd2..7a9de2e 100644
> --- a/arch/x86/perfmon/perfmon_amd64.c
> +++ b/arch/x86/perfmon/perfmon_amd64.c
> @@ -140,106 +140,12 @@ static struct pfm_context *pfm_nb_task_owner;
>
> static struct pfm_pmu_config pfm_amd64_pmu_conf;
>
> -/* Functions for accessing extended PCI config space. Can be removed
> - when Kernel API exists. */
> -extern spinlock_t pci_config_lock;
> -
> -#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
> - (0x80000000 | ((reg & 0xF00) << 16) | ((bus & 0xFF) << 16) \
> - | (devfn << 8) | (reg & 0xFC))
> -
> #define is_ibs_pmc(x) (x == 4 || x == 5)
>
> -static int pci_read(unsigned int seg, unsigned int bus,
> - unsigned int devfn, int reg, int len, u32 *value)
> -{
> - unsigned long flags;
> -
> - if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
> - *value = -1;
> - return -EINVAL;
> - }
> -
> - spin_lock_irqsave(&pci_config_lock, flags);
> -
> - outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
> -
> - switch (len) {
> - case 1:
> - *value = inb(0xCFC + (reg & 3));
> - break;
> - case 2:
> - *value = inw(0xCFC + (reg & 2));
> - break;
> - case 4:
> - *value = inl(0xCFC);
> - break;
> - }
> -
> - spin_unlock_irqrestore(&pci_config_lock, flags);
> -
> - return 0;
> -}
> -
> -static int pci_write(unsigned int seg, unsigned int bus,
> - unsigned int devfn, int reg, int len, u32 value)
> -{
> - unsigned long flags;
> -
> - if ((bus > 255) || (devfn > 255) || (reg > 4095))
> - return -EINVAL;
> -
> - spin_lock_irqsave(&pci_config_lock, flags);
> -
> - outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
> -
> - switch (len) {
> - case 1:
> - outb((u8)value, 0xCFC + (reg & 3));
> - break;
> - case 2:
> - outw((u16)value, 0xCFC + (reg & 2));
> - break;
> - case 4:
> - outl((u32)value, 0xCFC);
> - break;
> - }
> -
> - spin_unlock_irqrestore(&pci_config_lock, flags);
> -
> - return 0;
> -}
> -
> -static inline int
> -pci_read_ext_config_dword(struct pci_dev *dev, int where, u32 *val)
> -{
> - return pci_read(0, dev->bus->number, dev->devfn, where, 4, val);
> -}
> -
> -static inline int
> -pci_write_ext_config_dword(struct pci_dev *dev, int where, u32 val)
> -{
> - return pci_write(0, dev->bus->number, dev->devfn, where, 4, val);
> -}
> -
> -static void pfm_amd64_enable_pci_ecs_per_cpu(void)
> -{
> -#define ENABLE_CF8_EXT_CFG (1ULL << 46)
> - u64 reg;
> - /* enable PCI extended config space */
> - rdmsrl(MSR_AMD64_NB_CFG, reg);
> - if (reg & ENABLE_CF8_EXT_CFG)
> - return;
> - reg |= ENABLE_CF8_EXT_CFG;
> - wrmsrl(MSR_AMD64_NB_CFG, reg);
> -}
> -
> static void pfm_amd64_setup_eilvt_per_cpu(void *info)
> {
> u8 lvt_off;
>
> - pfm_amd64_enable_pci_ecs_per_cpu();
> -
> /* program the IBS vector to the perfmon vector */
> lvt_off = setup_APIC_eilvt_ibs(LOCAL_PERFMON_VECTOR,
> APIC_EILVT_MSG_FIX, 0);
> @@ -267,9 +173,9 @@ static int pfm_amd64_setup_eilvt(void)
> if (!cpu_cfg)
> break;
> ++nodes;
> - pci_write_ext_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
> - | IBSCTL_LVTOFFSETVAL);
> - pci_read_ext_config_dword(cpu_cfg, IBSCTL, &value);
> + pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
> + | IBSCTL_LVTOFFSETVAL);
> + pci_read_config_dword(cpu_cfg, IBSCTL, &value);
> if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
> PFM_DBG("Failed to setup IBS LVT offset, "
> "IBSCTL = 0x%08x", value);
> --
> 1.5.5.4
>
>
>
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