Hi Stephane,
This patch is an updated version of the previously posted patch that
fixes the bug that PMU exceptions were not disabled when the context is
in MASKED mode. In addition, I removed an extraneous deletion of a
blank line.
Regards,
- Corey
--
Corey Ashford
Software Engineer
IBM Linux Technology Center, Linux Toolchain
Beaverton, OR
503-578-3507
[EMAIL PROTECTED]
This patch makes sure that PMU exceptions are disabled while the context
is masked on POWER4 and POWER6 processors. A similar patch was made in January
for POWER5, and it was an error to not make the same change for these other
two processors.
In addition to that fix, some comments were cleaned up a little in the POWER6
version.
Index: linux-2.6/arch/powerpc/perfmon/perfmon_power6.c
===================================================================
--- linux-2.6.orig/arch/powerpc/perfmon/perfmon_power6.c 2008-07-15
16:46:57.000000000 -0400
+++ linux-2.6/arch/powerpc/perfmon/perfmon_power6.c 2008-07-15
16:49:41.000000000 -0400
@@ -412,12 +412,16 @@
pfm_interrupt_handler(instruction_pointer(regs), regs);
mmcr0 = mfspr(SPRN_MMCR0);
- /* Reset the perfmon trigger. */
- mmcr0 |= MMCR0_PMXE;
/*
- * We must clear the PMAO bit on some (GQ) chips. Just do it
- * all the time.
+ * Reset the perfmon trigger if
+ * not in masking mode.
+ */
+ if (ctx->state != PFM_CTX_MASKED)
+ mmcr0 |= MMCR0_PMXE;
+
+ /*
+ * Clear the PMU Alert Occurred bit
*/
mmcr0 &= ~MMCR0_PMAO;
Index: linux-2.6/arch/powerpc/perfmon/perfmon_power4.c
===================================================================
--- linux-2.6.orig/arch/powerpc/perfmon/perfmon_power4.c 2008-07-15
16:46:57.000000000 -0400
+++ linux-2.6/arch/powerpc/perfmon/perfmon_power4.c 2008-07-15
16:56:46.000000000 -0400
@@ -232,8 +232,13 @@
pfm_interrupt_handler(instruction_pointer(regs), regs);
mmcr0 = mfspr(SPRN_MMCR0);
- /* Reset the perfmon trigger. */
- mmcr0 |= MMCR0_PMXE;
+
+ /*
+ * Reset the perfmon trigger if
+ * not in masking mode.
+ */
+ if (ctx->state != PFM_CTX_MASKED)
+ mmcr0 |= MMCR0_PMXE;
/*
* We must clear the PMAO bit on some (GQ) chips. Just do it
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