Hello
The patch below (against the linux kernel) is needed on older SPARC
machines in order to use perfmon2. Without the patch, the machines will
actually panic at boot as they try to run strcmp() on uninitialized
memory as the pmu name is never set.
With this patch, I can use perfmon2 on an UltraSPARC2 based machine I
have.
Unfortunately the UltraSPARC2 does not have a pmu interrupt :(
Would it make sense at some point to have a common infrastructure for
using sampling to attempt to estimate 64-bit counts on machines without an
overflow interrupt? More machines than I expected have this problem.
Also, I am still working on the proper fix for Niagara to handle overflow
properly. It should be possible, I just haven't had time to work on it.
Thanks
Vince
--- arch/sparc64/kernel/cpu.c.orig 2008-09-11 11:17:56.000000000 -0400
+++ arch/sparc64/kernel/cpu.c 2008-09-11 11:17:23.000000000 -0400
@@ -50,17 +50,17 @@
#define NSPARCFPU ARRAY_SIZE(linux_sparc_fpu)
static struct cpu_iu_info linux_sparc_chips[] = {
- { 0x17, 0x10, "TI UltraSparc I (SpitFire)"},
- { 0x22, 0x10, "TI UltraSparc I (SpitFire)"},
- { 0x17, 0x11, "TI UltraSparc II (BlackBird)"},
- { 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
- { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
- { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
- { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
- { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
- { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
- { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
- { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
+ { 0x17, 0x10, "TI UltraSparc I (SpitFire)", "ultra12"},
+ { 0x22, 0x10, "TI UltraSparc I (SpitFire)", "ultra12"},
+ { 0x17, 0x11, "TI UltraSparc II (BlackBird)", "ultra12"},
+ { 0x17, 0x12, "TI UltraSparc IIi (Sabre)", "ultra12"},
+ { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"},
+ { 0x3e, 0x14, "TI UltraSparc III (Cheetah)", "ultra3"},
+ { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"},
+ { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"},
+ { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)", "ultra4"},
+ { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"},
+ { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3+"},
};
#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips)
@@ -142,6 +142,7 @@
manuf, impl);
}
sparc_cpu_type = "Unknown CPU";
+ sparc_pmu_type = "Unknown PMU";
}
for (i = 0; i < NSPARCFPU; i++) {
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