This patch adds a counter off value that specifies how to turn a specific 
counter off for generic powerpc. 
This is necessary because ppc970 arches do not use 0b00000 as an off value.
This libpfm patch requires the "*perfmon2 add support for ppc970 processors" 
kernel patch*:
http://sourceforge.net/mailarchive/message.php?msg_name=1226015978-19965-1-git-send-email-arges%40linux.vnet.ibm.com

Index: lib/pfmlib_gen_powerpc.c
===================================================================
RCS file: /cvsroot/perfmon2/libpfm/lib/pfmlib_gen_powerpc.c,v
retrieving revision 1.7
diff -r1.7 pfmlib_gen_powerpc.c
371a372,413
> static unsigned long long 
> power4_mmcr0_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
>       0, /* PMC1 */
>       0, /* PMC2 */
>       0,
>       0,
>       0,
>       0,
>       0,
>       0
> };
> static unsigned long long 
> power4_mmcr1_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
>       0,
>       0,
>       0, /* PMC3 */
>       0, /* PMC4 */
>       0, /* PMC5 */
>       0, /* PMC6 */
>       0, /* PMC7 */
>       0  /* PMC8 */
> };
> 
> static unsigned long long 
> ppc970_mmcr0_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
>       0x8UL << (63 - 55), /* PMC1 */
>       0x8UL << (63 - 62), /* PMC2 */
>       0,
>       0,
>       0,
>       0,
>       0,
>       0
> };
> static unsigned long long 
> ppc970_mmcr1_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
>       0,
>       0,
>       0x8UL << (63 - 36), /* PMC3 */
>       0x8UL << (63 - 41), /* PMC4 */
>       0x8UL << (63 - 46), /* PMC5 */
>       0x8UL << (63 - 51), /* PMC6 */
>       0x8UL << (63 - 56), /* PMC7 */
>       0x8UL << (63 - 61)  /* PMC8 */
> };
> 
386,387c428,429
<         0,
<         0
---
>       0,
>       0
389a432,448
> static unsigned long long 
> power5_mmcr0_counter_off_val[POWER5_NUM_EVENT_COUNTERS] = {
>       0,
>       0,
>       0,
>       0,
>       0,
>       0
> };
> 
> static unsigned long long 
> power5_mmcr1_counter_off_val[POWER5_NUM_EVENT_COUNTERS] = {
>       0, /* PMC1 */
>       0, /* PMC2 */
>       0, /* PMC3 */
>       0, /* PMC4 */
>       0,
>       0
> };
395a455,456
> static unsigned long long *mmcr0_counter_off_val;
> static unsigned long long *mmcr1_counter_off_val;
466a528
> 
493,494c555,556
<                        * This counter is not used, so zero out that
<                        * selector
---
>                        * This counter is not used, so set that
>                        * selector to its off value.
496a559
>                       mmcr0_val |= mmcr0_counter_off_val[i];  
497a561
>                       mmcr1_val |= mmcr1_counter_off_val[i];  
553c617
<               
---
>       
575c639
<               gen_powerpc_support.pmu_type = PFMLIB_POWER4_PMU;          
---
>               gen_powerpc_support.pmu_type = PFMLIB_PPC970_PMU;          
583a648,649
>               mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val;
>               mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val;
596a663,664
>               mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val;
>               mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val;
609a678,679
>               mmcr0_counter_off_val = power4_mmcr0_counter_off_val;
>               mmcr1_counter_off_val = power4_mmcr1_counter_off_val;
622a693,694
>               mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
>               mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
634a707,708
>               mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
>               mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
654a729,730
>               mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
>               mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
657a734
> 

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