Index: pfmon_util_mips64.c
===================================================================
RCS file: /cvsroot/perfmon2/pfmon/pfmon/pfmon_util_mips64.c,v
retrieving revision 1.13
diff -u -p -r1.13 pfmon_util_mips64.c
--- pfmon_util_mips64.c	19 May 2008 13:48:21 -0000	1.13
+++ pfmon_util_mips64.c	23 Jan 2009 09:11:25 -0000
@@ -33,6 +33,7 @@
 #include <sys/ptrace.h>
 #include <sys/user.h>
 #include <sys/time.h>
+#include <link.h>
 
 #include "pfmon.h"
 
@@ -53,6 +54,7 @@ static int is_delay_slot(pid_t pid, unsi
 {
   unsigned int op;
   unsigned long val;
+  unsigned long long val64;
 
   vbprintf("Checking for branch with delay slot at 0x%lx\n",address-4);
   /* Look to see if we are in a delay slot */
@@ -61,11 +63,14 @@ static int is_delay_slot(pid_t pid, unsi
     warning("set cannot peek[%d] %s\n", pid, strerror(errno));
     return 0;
   }
-
+  val64 = val;
 #if __BYTE_ORDER == __LITTLE_ENDIAN
   op = val & 0xffffffff;
 #elif __BYTE_ORDER == __BIG_ENDIAN
-  op = (val & 0xffffffff00000000) >> 32;
+  if (sizeof(val) == 8)
+  	op = (val64 & 0xffffffff00000000) >> 32;
+  else
+  	op = val & 0xffffffff;
 #else
 #error "cannot determine endianess"
 #endif
@@ -142,7 +147,7 @@ pfmon_mips64_set_breakpoint(pid_t pid, p
   }
   
   DPRINT(("DB%d START%d trgt instruction = 0x%016lx at 0x%lx\n",
-	dbreg, trg->trg_attr_start, val, address));
+	dbreg, trg->brk_type == PFMON_TRIGGER_START, val, address));
   if (val == bpi()) {
     warning("breakpoint already set at 0x%lx\n", address);
     return -1;
@@ -154,7 +159,7 @@ pfmon_mips64_set_breakpoint(pid_t pid, p
   }
 
   vbprintf("[%d] setting code breakpoint DB%d, START%d @%p\n", 
-	   pid, dbreg, trg->trg_attr_start,
+	   pid, dbreg, trg->brk_type == PFMON_TRIGGER_START,
 	   address);
   r = ptrace(PTRACE_POKETEXT, pid, address, bpi());
   if (r == -1) {
@@ -172,7 +177,7 @@ pfmon_mips64_set_breakpoint(pid_t pid, p
 
   bpoints[dbreg].address = address;
   bpoints[dbreg].val = val;
-  bpoints[dbreg].is_start = trg->trg_attr_start;
+  bpoints[dbreg].is_start = trg->brk_type == PFMON_TRIGGER_START;
 
   return 0;
 }
@@ -195,7 +200,7 @@ pfmon_mips64_clear_breakpoint(pid_t pid,
   val = bpoints[dbreg].val;
 
   vbprintf("[%d] clearing code breakpoint DB%d, START%d, @%p\n", 
-	   pid,dbreg,trg->trg_attr_start,
+	   pid,dbreg,trg->brk_type == PFMON_TRIGGER_START,
 	   address);
 
   r = ptrace(PTRACE_PEEKTEXT, pid, address, 0);
@@ -204,7 +209,7 @@ pfmon_mips64_clear_breakpoint(pid_t pid,
   }
  
   DPRINT(("DB%d START%d curr instruction = 0x%016lx at 0x%lx, writing 0x%016lx\n",
-	 dbreg,trg->trg_attr_start,r,address,val));
+	 dbreg,trg->brk_type == PFMON_TRIGGER_START,r,address,val));
   
   r = ptrace(PTRACE_POKETEXT, pid, address, val);
   if (r == -1) {
@@ -297,7 +302,7 @@ pfmon_resume_after_code_breakpoint(pid_t
 
   /* Only set the start breakpoint again if we have reached the stop breakpoint. 
      The stop breakpoint setting the start breakpoint again is handled in pfmon_task.c */
-  if (trg->trg_attr_start)
+  if (trg->brk_type == PFMON_TRIGGER_START)
     pfmon_mips64_set_breakpoint(pid, trg);
 
   /* End segment for pfmon_task.c */
@@ -313,7 +318,7 @@ pfmon_resume_after_data_breakpoint(pid_t
 void
 pfmon_arch_initialize(void)
 {
-  pfmlib_regmask_t r_pmcs;
+  pfmlib_regmask_t r_pmcs, r_pmds;
   
   /* MIPS using SW breakpoints only */
   options.opt_hw_brk = 0;
@@ -322,7 +327,7 @@ pfmon_arch_initialize(void)
    * a side effect of this call is to create a dummy
    * context which does trigger the kernel module load
    */
-  pfmon_detect_unavail_pmcs(&r_pmcs);
+  pfmon_detect_unavail_regs(&r_pmcs, &r_pmds);
 
   options.opt_support_gen = 0;
   options.libpfm_generic  = 0;