This patch updates revision flags and descriptions of some events. No
major changes, just an update mainly for the K8:
BIOS and Kernel Developer's Guide, #26094, Revision: 3.30
BIOS and Kernel Developer's Guide, #32559, Revision: 3.12
Signed-off-by: Robert Richter <robert.rich...@amd.com>
---
lib/amd64_events_fam10h.h | 8 +++++++-
lib/amd64_events_k8.h | 45 +++++++++++++++++++++++++++++++++++++--------
lib/pfmlib_amd64_priv.h | 3 +++
3 files changed, 47 insertions(+), 9 deletions(-)
diff --git a/lib/amd64_events_fam10h.h b/lib/amd64_events_fam10h.h
index 9f14fac..be893a2 100644
--- a/lib/amd64_events_fam10h.h
+++ b/lib/amd64_events_fam10h.h
@@ -438,7 +438,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
.pme_code = 0x45,
.pme_desc = "L1 DTLB Miss and L2 DTLB Hit",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO,
- .pme_numasks = 4,
+ .pme_numasks = 5,
.pme_umasks = {
{ .pme_uname = "L2_4K_TLB_HIT",
.pme_udesc = "L2 4K TLB hit",
@@ -448,6 +448,11 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
.pme_udesc = "L2 2M TLB hit",
.pme_ucode = 0x02,
},
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x03,
+ .pme_uflags = PFMLIB_AMD64_TILL_FAM10H_REV_B,
+ },
{ .pme_uname = "L2_1G_TLB_HIT",
.pme_udesc = "L2 1G TLB hit",
.pme_ucode = 0x04,
@@ -456,6 +461,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
.pme_ucode = 0x07,
+ .pme_uflags = PFMLIB_AMD64_FAM10H_REV_C,
},
},
},
diff --git a/lib/amd64_events_k8.h b/lib/amd64_events_k8.h
index d5b2413..c969537 100644
--- a/lib/amd64_events_k8.h
+++ b/lib/amd64_events_k8.h
@@ -38,6 +38,12 @@
* 0Fh Processors, Publication # 32559, Revision: 3.08, Issue Date:
* July 2007
*
+ * Feb 26 2009 -- Robert Richter, robert.rich...@amd.com
+ *
+ * Updates and fixes of some revision flags and descriptions according
+ * to these documents:
+ * BIOS and Kernel Developer's Guide, #26094, Revision: 3.30
+ * BIOS and Kernel Developer's Guide, #32559, Revision: 3.12
*/
static pme_amd64_entry_t amd64_k8_pe[]={
@@ -489,19 +495,26 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_code = 0x7F,
.pme_desc = "L2 Fill/Writeback",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO,
- .pme_numasks = 3,
+ .pme_numasks = 4,
.pme_umasks = {
{ .pme_uname = "L2_FILLS",
.pme_udesc = "L2 fills (victims from L1 caches, TLB page
table walks and data prefetches)",
.pme_ucode = 0x01,
},
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x01,
+ .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_E,
+ },
{ .pme_uname = "L2_WRITEBACKS",
.pme_udesc = "L2 Writebacks to system.",
.pme_ucode = 0x02,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
.pme_ucode = 0x03,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
},
},
@@ -603,7 +616,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
},
/* 52 */{.pme_name = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
.pme_code = 0xCB,
- .pme_desc = "Retired MMX Instructions",
+ .pme_desc = "Retired MMX/FP Instructions",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO,
.pme_numasks = 5,
.pme_umasks = {
@@ -864,24 +877,28 @@ static pme_amd64_entry_t amd64_k8_pe[]={
/* 78 */{.pme_name = "THERMAL_STATUS_AND_ECC_ERRORS",
.pme_code = 0xE8,
.pme_desc = "Thermal Status and ECC Errors",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
- .pme_numasks = 6,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_K8_REV_E,
+ .pme_numasks = 7,
.pme_umasks = {
{ .pme_uname = "CLKS_CPU_ACTIVE",
.pme_udesc = "Number of clocks CPU is active when HTC is
active",
.pme_ucode = 0x01,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
{ .pme_uname = "CLKS_CPU_INACTIVE",
.pme_udesc = "Number of clocks CPU clock is inactive when HTC
is active",
.pme_ucode = 0x02,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
{ .pme_uname = "CLKS_DIE_TEMP_TOO_HIGH",
- .pme_udesc = "Number of clocks when die temperature is higher
than the software high temperature",
+ .pme_udesc = "Number of clocks when die temperature is higher
than the software high temperature threshold",
.pme_ucode = 0x04,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
{ .pme_uname = "CLKS_TEMP_THRESHOLD_EXCEEDED",
.pme_udesc = "Number of clocks when high temperature
threshold was exceeded",
.pme_ucode = 0x08,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
{ .pme_uname = "DRAM_ECC_ERRORS",
.pme_udesc = "Number of correctable and Uncorrectable DRAM
ECC errors",
@@ -889,7 +906,13 @@ static pme_amd64_entry_t amd64_k8_pe[]={
},
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x80,
+ .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_E,
+ },
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
.pme_ucode = 0x8F,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
},
},
@@ -984,11 +1007,11 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_ucode = 0x02,
},
{ .pme_uname = "POSTED_WRITE_BYTE",
- .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line
DMA writes, size varies; also flushes of",
+ .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line
DMA writes, size varies; also flushes of partially-filled Write Combining
buffer",
.pme_ucode = 0x04,
},
{ .pme_uname = "POSTED_WRITE_DWORD",
- .pme_udesc = "Posted SzWr Dword (1-16 dwords) Block-oriented
DMA writes, often cache-line sized; also",
+ .pme_udesc = "Posted SzWr Dword (1-16 dwords) Block-oriented
DMA writes, often cache-line sized; also processor Write Combining buffer
flushes",
.pme_ucode = 0x08,
},
{ .pme_uname = "READ_BYTE_4_BYTES",
@@ -1013,7 +1036,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_code = 0xEC,
.pme_desc = "Probe Responses and Upstream Requests",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO,
- .pme_numasks = 8,
+ .pme_numasks = 9,
.pme_umasks = {
{ .pme_uname = "MISS",
.pme_udesc = "Probe miss",
@@ -1039,6 +1062,11 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_udesc = "Upstream non-display refresh reads",
.pme_ucode = 0x20,
},
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x3F,
+ .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_C,
+ },
{ .pme_uname = "UPSTREAM_WRITES",
.pme_udesc = "Upstream writes",
.pme_ucode = 0x40,
@@ -1047,6 +1075,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
.pme_ucode = 0x7F,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_D,
},
},
},
diff --git a/lib/pfmlib_amd64_priv.h b/lib/pfmlib_amd64_priv.h
index ccf3f8d..7b300f0 100644
--- a/lib/pfmlib_amd64_priv.h
+++ b/lib/pfmlib_amd64_priv.h
@@ -95,9 +95,12 @@ static const char *amd64_cpu_strs[] = {
#define PFMLIB_AMD64_FROM_REV(rev) ((rev)<<8)
#define PFMLIB_AMD64_TILL_REV(rev) ((rev)<<16)
#define PFMLIB_AMD64_NOT_SUPP 0x1ff00
+#define PFMLIB_AMD64_TILL_K8_REV_C PFMLIB_AMD64_TILL_REV(AMD64_K8_REV_C)
#define PFMLIB_AMD64_K8_REV_D PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_D)
#define PFMLIB_AMD64_K8_REV_E PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_E)
+#define PFMLIB_AMD64_TILL_K8_REV_E PFMLIB_AMD64_TILL_REV(AMD64_K8_REV_E)
#define PFMLIB_AMD64_K8_REV_F PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_F)
+#define PFMLIB_AMD64_TILL_FAM10H_REV_B
PFMLIB_AMD64_TILL_REV(AMD64_FAM10H_REV_B)
#define PFMLIB_AMD64_FAM10H_REV_C
PFMLIB_AMD64_FROM_REV(AMD64_FAM10H_REV_C)
#define PFMLIB_AMD64_TILL_FAM10H_REV_C
PFMLIB_AMD64_TILL_REV(AMD64_FAM10H_REV_C)
#define PFMLIB_AMD64_FAM10H_REV_D
PFMLIB_AMD64_FROM_REV(AMD64_FAM10H_REV_D)
--
1.6.1.3
------------------------------------------------------------------------------
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