Juan, Monitoring over a range of code or data addresses is not as flexible as one would wish. As you realize range restriction is implemented using the debug registers. The range of addresses is specified using a bitmask and NOT a length. Therefore there are some strict alignment constraints.
You don't want to monitor outside of the range. Thus, libpfm must make sure the range is covered exactly. To achieve this goal, libpfm may use more than one pair of debug registers to breakdown the range into small power of two ranges. But if it does that for one range, it may not have debug registers left to cover yet another range. That may be what you are running into. Since Itanium2, there is another way of configuring the debug registers to try and address the alignment issue. It is called: fine mode. This time you do not use a bitmask to specify the range, you use two pairs of debug registers: one to designate the start position and one for the end position. But there are some other constraints (and bugs) which I don't quite recall. I suggest you try playing with the alignment of your functions. 2009/4/21 Juan Ángel Lorenzo <jalmailingli...@gmail.com>: > Hi, > > After checking the data range restriction example included with the > library (mont_rr.c, in the old_interface_ia64_examples directory) I've > been trying to modify it to cover two different data ranges. The example > has two arrays already defined: test_data and test_data_fake. I define a > third one, test_data_fake2, and I get the start and end ranges, as done > for test_data: > > test_data_fake2 = > (test_data_t*)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); > > range_start_fake2 = (unsigned long)test_data_fake2; > range_end_fake2 = range_start_fake2 + \ > sizeof(test_data_t)*TEST_DATA_COUNT; > > > Afterwards, I try to use a pair of debug registers to cover this new > array: > > mont_inp.pfp_mont_drange.rr_limits[1].rr_start = range_start_fake2; > mont_inp.pfp_mont_drange.rr_limits[1].rr_end = range_end_fake2; > > but I get an error message when I run the code: "cannot configure > events: too many data ranges". Using the next pair (rr_limits[2]) I > don't get any error, but I got the following output: > > > [PMC5(pmc5)=0x200ce08 m=0 e=0 s=0 i=0 thres=0 all=0 es=0xce plm=8 > umask=0x0 pm=0 ism=0x2 oi=0] MISALIGNED_LOADS_RETIRED > [PMD5(pmd5)] > > [0x6000000000004010-0x6000000000004110): 4 register pair(s) > start offset: -0x10 end_offset: +0x0 > > brp0: db0: 0x6000000000004080 db1: plm=0x8 mask=0x00ffffffffffff80 > end=0x60000000000040ff > brp1: db2: 0x6000000000004040 db3: plm=0x8 mask=0x00ffffffffffffc0 > end=0x600000000000407f > brp2: db4: 0x6000000000004000 db5: plm=0x8 mask=0x00ffffffffffffc0 > end=0x600000000000403f > brp3: db6: 0x6000000000004100 db7: plm=0x8 mask=0x00fffffffffffff0 > end=0x600000000000410f > > [PMC41(pmc41)=0x1e078f6f6f6f6 cfg_dtag0=2 cfg_dtag1=2 cfg_dtag2=2 > cfg_dtag3=2 ena_dbrp0=1 ena_dbrp1=1 ena_dbrp2=1 ena_dbrp3=1] > > data range : [0x6000000000004010-0x6000000000004110): 4 pair of debug > registers used > start_offset:-0x10 end_offset:+0x0 > Fake data range2 : [0x6000000000004230-0x6000000000004330) > start_offset:-0x0 end_offset:+0x0 > fake data range: [0x6000000000004120-0x6000000000004220) > > So it looks the test_data_fake2 is in the range > (0x60...4230,0x60...4330), but the debug registers (db0-db7) only show > coverage from addresses 0x6...4080 to 0x6...410f. > > Any hint of what's wrong? Isn't it possible to cover two data ranges at > the same time in Montecito/Montvale?. Perfmon2 documentation says that > "Up to 4 ranges can be defined" in Montecito. > > Thanks in advance, > Juan > > > ------------------------------------------------------------------------------ > Stay on top of everything new and different, both inside and > around Java (TM) technology - register by April 22, and save > $200 on the JavaOne (SM) conference, June 2-5, 2009, San Francisco. > 300 plus technical and hands-on sessions. Register today. > Use priority code J9JMT32. http://p.sf.net/sfu/p > _______________________________________________ > perfmon2-devel mailing list > perfmon2-devel@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/perfmon2-devel > ------------------------------------------------------------------------------ Stay on top of everything new and different, both inside and around Java (TM) technology - register by April 22, and save $200 on the JavaOne (SM) conference, June 2-5, 2009, San Francisco. 300 plus technical and hands-on sessions. Register today. Use priority code J9JMT32. http://p.sf.net/sfu/p _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
