Ken, Alternatively, I think there is also an errata that seem to describe the problem with L1D_CACHE_*.
Look in http://download.intel.com/design/processor/specupdt/320836.pdf And erratum AAJ105. On Wed, Jul 15, 2009 at 3:26 AM, stephane eranian<eran...@googlemail.com> wrote: > Ken, > > On Fri, Jul 3, 2009 at 10:01 PM, Kenneth Hoste<kenneth.ho...@ugent.be> wrote: >> >> On Jul 1, 2009, at 07:03 , stephane eranian wrote: >> >>> Kenneth, >>> >>> Let me check on this with Intel. >> >> Thanks! Any news yet? >> > > I can confirm that the following events do indeed overcount on Intel Core i7: > - L1D_CACHE_LOCK : overcounts by 3x > - L1D_CACHE_LD : overcounts because "This event counts load > uops at dispatch. Consequently loads " > which are blocked and then > re-dispatched will be counted multiple times." > - L1D_CACHE_ST : overcounts for the same reason as L1D_CACHE_LD > > For D-cache misses, it is recommended you use MEM_LOAD_RETIRED which > is what you did. > As for your approximation using this event, you may also want to add HIT_LFB. > > I have not yet received confirmation about your initial posting about > L1I:MISSES but it is likely > it also overcounts. > > Those issues are known but the SDM Vol3b has not yet been updated to > reflect them. > > Thanks for your patience. > ------------------------------------------------------------------------------ Enter the BlackBerry Developer Challenge This is your chance to win up to $100,000 in prizes! For a limited time, vendors submitting new applications to BlackBerry App World(TM) will have the opportunity to enter the BlackBerry Developer Challenge. See full prize details at: http://p.sf.net/sfu/Challenge _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
