Hello
here are a few more MIPS issues. Sorry it is not broken out properly, but
I defend my PhD next week so I am a bit busy. Wantd to send this out
before I forgot about it.
On MIPS R12000 the event mask is 5 bits, not 4. In theory this is
backwards compatible, at least to R10000. The way things currently are,
the top bit is lost and thus the top 16 events alias to the bottom ones.
This took me a while to track down, bitfields can be annoying. I vaguely
feel like this issue might have come up before in the past, but my search
of the archives wasn't turning it up.
The other issue is one where the debug message was printing wrong values
when compiled on a 32-bit host. Not sure if it's the right fix.
MIPS support for perfmon2 indeed still works, although in sampled mode it
gets stuck on floating point programs, haven't had time to find out why.
I also was using prefmon2 on an older itanium machine with only the stock
perfmon support. That mostly works too, though there are a few unused
variable warnings that turn to errors due to -Werror being on.
Vince
diff -u -r libpfm-3.9/include/perfmon/pfmlib_gen_mips64.h
libpfm-3.9-vmw/include/perfmon/pfmlib_gen_mips64.h
--- libpfm-3.9/include/perfmon/pfmlib_gen_mips64.h 2008-05-30
07:23:03.000000000 -0400
+++ libpfm-3.9-vmw/include/perfmon/pfmlib_gen_mips64.h 2009-12-04
17:02:35.000000000 -0500
@@ -61,8 +61,8 @@
unsigned long sel_sup:1; /* supervisor level */
unsigned long sel_usr:1; /* user level */
unsigned long sel_int:1; /* enable intr */
- unsigned long sel_event_mask:4; /* event mask */
- unsigned long sel_res1:23; /* reserved */
+ unsigned long sel_event_mask:5; /* event mask */
+ unsigned long sel_res1:22; /* reserved */
unsigned long sel_res2:32; /* reserved */
} perfsel;
} pfm_gen_mips64_sel_reg_t;
@@ -73,8 +73,8 @@
uint64_t val; /* complete register
value */
struct {
unsigned long sel_res2:32; /* reserved */
- unsigned long sel_res1:23; /* reserved */
- unsigned long sel_event_mask:4; /* event mask */
+ unsigned long sel_res1:22; /* reserved */
+ unsigned long sel_event_mask:5; /* event mask */
unsigned long sel_int:1; /* enable intr */
unsigned long sel_usr:1; /* user level */
unsigned long sel_sup:1; /* supervisor level */
diff -u -r libpfm-3.9/lib/pfmlib_gen_mips64.c
libpfm-3.9-vmw/lib/pfmlib_gen_mips64.c
--- libpfm-3.9/lib/pfmlib_gen_mips64.c 2008-08-07 14:57:32.000000000 -0400
+++ libpfm-3.9-vmw/lib/pfmlib_gen_mips64.c 2009-12-04 17:05:49.000000000
-0500
@@ -209,9 +209,9 @@
reg.sel_event_mask = (gen_mips64_pe[e[j].event].pme_code >> (cntr*8)) &
0xff;
pc[j].reg_value = reg.val;
pc[j].reg_addr = cntr*2;
- pc[j].reg_num = cntr;
+ pc[j].reg_num = cntr;
- __pfm_vbprintf("[CP0_25_%u(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d
os=%d sup=%d exl=%d int=1] %s\n",
+ __pfm_vbprintf("[CP0_25_%"PRIx64"(pmc%u)=0x%"PRIx64" event_mask=0x%x
usr=%d os=%d sup=%d exl=%d int=1] %s\n",
pc[j].reg_addr,
pc[j].reg_num,
pc[j].reg_value,
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