Hi,
On Thu, Dec 17, 2009 at 1:41 AM, Josh Stone <jist...@redhat.com> wrote:
> On 12/15/2009 07:53 PM, jiey...@mail.ustc.edu.cn wrote:
>> Hi,Stephane.
>>
>> I have been tracing your work in perfmon2/3,and doing some similar work in
>> my thesis.
>>
>> I extended the task_struct with pmu-related context and added support to
>> save/restore it in __switch_to,all under linux 2.6.30.
>> Then I encounter a problem, when the following code is running with counting
>> disabled.
>> ...
>> {
>> wrmsrl(pmu_reg->counter_addr,pmu_reg->counter);
>> rdmsrl(pmu_reg->counter_addr,co);
>> }
>> so far what really confusing is that quite often values of pmu_reg->counter
>> and co
> are not equal，and the later one would suddenly become really
> large（e.g. the high 8 bits of counter register are ff），i.e. the value
> written into counter register is wrong
>
> Are you aware of the sign-extension on PMC writes? Here's a quote from
> the Intel manual, volume 3B section 30.2.1.1:
>
> "The bit width of an IA32_PMCx MSR is reported using the
> CPUID.0AH:EAX[23:16]. Bits beyond the width of the programmable
> counter are undefined, and are ignored when written to. On write
> operations, the lower-order 32 bits of each MSR may be written with
> any value, and the high-order bits are sign-extended according to the
> value of bit 31. The bit width for read operations is reported using
> CPUID."
>
Josh is right. sign-extension is your problem.
n, I modified the code to the following version, like
>> {
>> again:
>> wrmsrl(pmu_reg->counter_addr,pmu_reg->counter & PMUC_MASK);
>> rdmsrl(pmu_reg->counter_addr,co);
>> if(pmu_reg->counter!=co)
>> goto again;
>> }
>>
>> This time, the system runs into a state of unhalted busy with no reaction
>> and no oops printing.
>> And why? I know you shoule be familiar with these issues, so could any help?
>
> There's no oops because nothing really failed -- it's an infinite loop.
>
> This could work if PMUC_MASK is 0x7fffffff, but you also need to use the
> mask in the comparison.
>
>
> Josh
>
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