On Thu, Jan 21, 2010 at 11:46 AM, Peter Zijlstra <pet...@infradead.org> wrote:
> On Thu, 2010-01-21 at 11:43 +0100, Stephane Eranian wrote:
>> On Thu, Jan 21, 2010 at 11:36 AM, Peter Zijlstra <pet...@infradead.org>
>> wrote:
>> > On Mon, 2010-01-18 at 10:58 +0200, Stephane Eranian wrote:
>> >> void hw_perf_enable(void)
>> >> {
>> >
>> >
>> >> + cpuc->n_added = 0;
>> >> + perf_events_lapic_init();
>> >
>> > Just wondering, why do we need that lapic_init() there?
>> >
>> I think I picked it up from x86_pmu_enable(). I don't think
>> you necessarily need it here. Not clear to me why it was
>> in x86_pmu_enable() to begin with.
>
> Right, wondering about the same ;-)
>
I suspect this is because on Intel, you need to re-initialize
the APIC LVT entry on PMU interrupt. You don't have to do this
on AMD.
But then, this should be done when you initialize the
PMU for the first event and on every CPU and in the Intel
interrupt handler.
>> I will post a new version of the patch which fixes some bugs and
>> also implements true fast path (reuse of previous assignment). It turned
>> out, things were a bit more complicated than what I had in v5.
>
> Could you post a diff against your previous version, I just picked up
> -v5 and tidied a few things up and send it mingo wards (although it
> appears he hasn't picked it up yet).
>
Will do that shortly.
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