On Fri, 2010-01-22 at 11:33 -0600, John McCalpin wrote: > * Think of the system as having four performance monitors per core > *plus* four performance monitors for the "shared" structures on the > chip (L3, crossbar, HyperTransport links, memory controllers).
Would have been nice to have them as a separately addressable pmu instead of shadowing the logical cpu's pmu. But that's all ancient history of course.. > There is an additional hazard when working with early K8 processors -- > a hardware bug causes the counts of all shared counters to be reset to > zero any time any shared register is programmed. This makes > "protecting" users somewhat more difficult.... Could you qualify early k8 a bit more, it shouldn't be hard to add a quirk for a specific set of cpus to read/reset all counters before writing to the shared pmu. ------------------------------------------------------------------------------ Throughout its 18-year history, RSA Conference consistently attracts the world's best and brightest in the field, creating opportunities for Conference attendees to learn about information security's most important issues through interactions with peers, luminaries and emerging and established companies. http://p.sf.net/sfu/rsaconf-dev2dev _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
