On Tue, Mar 9, 2010 at 1:34 PM, heechul Yun <heechul....@gmail.com> wrote: > > > On Tue, Mar 9, 2010 at 3:06 PM, stephane eranian <eran...@googlemail.com> > wrote: >> >> On Tue, Mar 9, 2010 at 11:21 AM, heechul Yun <heechul....@gmail.com> >> wrote: >> > I am very sorry for the prior message which is sent accidentally during >> > writing. >> > I used perf_examples/task.c and performed the following simple >> > measurement >> > for 'ls' command several times. >> > >> > ./task ls -e "BR_INST_RETIRED" >> > 686804 BR_INST_RETIRED <-- first execution >> > 686803 BR_INST_RETIRED <-- second execution >> > 686805 BR_INST_RETIRED <-- third execution >> > . >> That's nothing major. It is in the noise. >> >> > ./task ls -e "MEM_STORE_RETIRED" >> > 226 MEM_STORE_RETIRED >> > 250 MEM_STORE_RETIRED >> > 217 MEM_STORE_RETIRED >> > ./task ls -e "INST_RETIRED" >> > 2830093 INST_RETIRED >> > 2830099 INST_RETIRED >> > 2830097 INST_RETIRED >> > >> > On the other hand, "inst_retired:stores" on core2duo always gave me the >> > same >> > number. >> >> Most likely it is because stores occur less frequently than branches. >> There are >> always interruptions going on when you measure, even just at the user >> level. >> > > Do you mean that even though I exclude kernel level events ( exclude_kernel > = 1) the interrupt handler portion of the events are counted? Could you > briefly explain what kind of interruptions destroy determinism?
There are several things you could do to try and narrow down a cause: - write a simple program which is deterministic (e.g., matrix add) - use the Intel PIN tool to count the exact number of instructions retired. - then compare the PIN count with the PMU count, that's the error margin - try changing the duration of the program to see how it impacts the wobbling I suspect there may be PMU leaks when you enter the kernel for an interrupt. ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
