Update from:
BIOS and Kernel Developer's Guide (BKDG) For AMD
Family 10h Processors, 31116 Rev 3.48 - April 22, 2010
Added:
* EventSelect 068h and EventSelect 069h (all models)
* EventSelect 4EDh (RevD)
Signed-off-by: Robert Richter <robert.rich...@amd.com>
---
lib/events/amd64_events_fam10h.h | 351 +++++++++++++++++++++++++++-----------
1 files changed, 254 insertions(+), 97 deletions(-)
diff --git a/lib/events/amd64_events_fam10h.h b/lib/events/amd64_events_fam10h.h
index 48a513b..a45dd87 100644
--- a/lib/events/amd64_events_fam10h.h
+++ b/lib/events/amd64_events_fam10h.h
@@ -25,6 +25,11 @@
/* History
*
+ * May 28 2010 -- Robert Richter, robert.rich...@amd.com:
+ *
+ * Update from: BIOS and Kernel Developer's Guide (BKDG) For AMD
+ * Family 10h Processors, 31116 Rev 3.48 - April 22, 2010
+ *
* Feb 06 2009 -- Robert Richter, robert.rich...@amd.com:
*
* Update for Family 10h RevD (Istanbul) from: BIOS and Kernel
@@ -694,7 +699,103 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 34 */{.name = "SYSTEM_READ_RESPONSES",
+/* 34 */{.name = "MAB_REQUESTS",
+ .code = 0x68,
+ .modmsk = AMD64_FAM10H_ATTRS,
+ .desc = "Average L1 refill latency for Icache and Dcache misses
(request count for cache refills)",
+ .numasks = 10,
+ .umasks = {
+ { .uname = "BUFFER_0",
+ .udesc = "Buffer 0",
+ .ucode = 0x00,
+ },
+ { .uname = "BUFFER_1",
+ .udesc = "Buffer 1",
+ .ucode = 0x01,
+ },
+ { .uname = "BUFFER_2",
+ .udesc = "Buffer 2",
+ .ucode = 0x02,
+ },
+ { .uname = "BUFFER_3",
+ .udesc = "Buffer 3",
+ .ucode = 0x03,
+ },
+ { .uname = "BUFFER_4",
+ .udesc = "Buffer 4",
+ .ucode = 0x04,
+ },
+ { .uname = "BUFFER_5",
+ .udesc = "Buffer 5",
+ .ucode = 0x05,
+ },
+ { .uname = "BUFFER_6",
+ .udesc = "Buffer 6",
+ .ucode = 0x06,
+ },
+ { .uname = "BUFFER_7",
+ .udesc = "Buffer 7",
+ .ucode = 0x07,
+ },
+ { .uname = "BUFFER_8",
+ .udesc = "Buffer 8",
+ .ucode = 0x08,
+ },
+ { .uname = "BUFFER_9",
+ .udesc = "Buffer 9",
+ .ucode = 0x09,
+ },
+ },
+ },
+/* 35 */{.name = "MAB_WAIT_CYCLES",
+ .code = 0x69,
+ .modmsk = AMD64_FAM10H_ATTRS,
+ .desc = "Average L1 refill latency for Icache and Dcache misses
(cycles that requests spent waiting for the refills)",
+ .numasks = 10,
+ .umasks = {
+ { .uname = "BUFFER_0",
+ .udesc = "Buffer 0",
+ .ucode = 0x00,
+ },
+ { .uname = "BUFFER_1",
+ .udesc = "Buffer 1",
+ .ucode = 0x01,
+ },
+ { .uname = "BUFFER_2",
+ .udesc = "Buffer 2",
+ .ucode = 0x02,
+ },
+ { .uname = "BUFFER_3",
+ .udesc = "Buffer 3",
+ .ucode = 0x03,
+ },
+ { .uname = "BUFFER_4",
+ .udesc = "Buffer 4",
+ .ucode = 0x04,
+ },
+ { .uname = "BUFFER_5",
+ .udesc = "Buffer 5",
+ .ucode = 0x05,
+ },
+ { .uname = "BUFFER_6",
+ .udesc = "Buffer 6",
+ .ucode = 0x06,
+ },
+ { .uname = "BUFFER_7",
+ .udesc = "Buffer 7",
+ .ucode = 0x07,
+ },
+ { .uname = "BUFFER_8",
+ .udesc = "Buffer 8",
+ .ucode = 0x08,
+ },
+ { .uname = "BUFFER_9",
+ .udesc = "Buffer 9",
+ .ucode = 0x09,
+ },
+ },
+ },
+/* 36 */{.name = "SYSTEM_READ_RESPONSES",
.code = 0x6C,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Northbridge Read Responses by Coherency State",
@@ -727,7 +828,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 35 */{.name = "QUADWORDS_WRITTEN_TO_SYSTEM",
+/* 37 */{.name = "QUADWORDS_WRITTEN_TO_SYSTEM",
.code = 0x6D,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Octwords Written to System",
@@ -744,12 +845,12 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 36 */{.name = "CPU_CLK_UNHALTED",
+/* 38 */{.name = "CPU_CLK_UNHALTED",
.code = 0x76,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU Clocks not Halted",
},
-/* 37 */{.name = "REQUESTS_TO_L2",
+/* 39 */{.name = "REQUESTS_TO_L2",
.code = 0x7D,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Requests to L2 Cache",
@@ -786,7 +887,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 38 */{.name = "L2_CACHE_MISS",
+/* 40 */{.name = "L2_CACHE_MISS",
.code = 0x7E,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L2 Cache Misses",
@@ -815,7 +916,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 39 */{.name = "L2_FILL_WRITEBACK",
+/* 41 */{.name = "L2_FILL_WRITEBACK",
.code = 0x7F,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L2 Fill/Writeback",
@@ -836,32 +937,32 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 40 */{.name = "INSTRUCTION_CACHE_FETCHES",
+/* 42 */{.name = "INSTRUCTION_CACHE_FETCHES",
.code = 0x80,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Instruction Cache Fetches",
},
-/* 41 */{.name = "INSTRUCTION_CACHE_MISSES",
+/* 43 */{.name = "INSTRUCTION_CACHE_MISSES",
.code = 0x81,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Instruction Cache Misses",
},
-/* 42 */{.name = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
+/* 44 */{.name = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
.code = 0x82,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Instruction Cache Refills from L2",
},
-/* 43 */{.name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
+/* 45 */{.name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
.code = 0x83,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Instruction Cache Refills from System",
},
-/* 44 */{.name = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
+/* 46 */{.name = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
.code = 0x84,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L1 ITLB Miss and L2 ITLB Hit",
},
-/* 45 */{.name = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
+/* 47 */{.name = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
.code = 0x85,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L1 ITLB Miss and L2 ITLB Miss",
@@ -882,32 +983,32 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 46 */{.name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
+/* 48 */{.name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
.code = 0x86,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Pipeline Restart Due to Instruction Stream Probe",
},
-/* 47 */{.name = "INSTRUCTION_FETCH_STALL",
+/* 49 */{.name = "INSTRUCTION_FETCH_STALL",
.code = 0x87,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Instruction Fetch Stall",
},
-/* 48 */{.name = "RETURN_STACK_HITS",
+/* 50 */{.name = "RETURN_STACK_HITS",
.code = 0x88,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Return Stack Hits",
},
-/* 49 */{.name = "RETURN_STACK_OVERFLOWS",
+/* 51 */{.name = "RETURN_STACK_OVERFLOWS",
.code = 0x89,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Return Stack Overflows",
},
-/* 50 */{.name = "INSTRUCTION_CACHE_VICTIMS",
+/* 52 */{.name = "INSTRUCTION_CACHE_VICTIMS",
.code = 0x8B,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Instruction Cache Victims",
},
-/* 51 */{.name = "INSTRUCTION_CACHE_LINES_INVALIDATED",
+/* 53 */{.name = "INSTRUCTION_CACHE_LINES_INVALIDATED",
.code = 0x8C,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Instruction Cache Lines Invalidated",
@@ -928,72 +1029,72 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 52 */{.name = "ITLB_RELOADS",
+/* 54 */{.name = "ITLB_RELOADS",
.code = 0x99,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "ITLB Reloads",
},
-/* 53 */{.name = "ITLB_RELOADS_ABORTED",
+/* 55 */{.name = "ITLB_RELOADS_ABORTED",
.code = 0x9A,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "ITLB Reloads Aborted",
},
-/* 54 */{.name = "RETIRED_INSTRUCTIONS",
+/* 56 */{.name = "RETIRED_INSTRUCTIONS",
.code = 0xC0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Instructions",
},
-/* 55 */{.name = "RETIRED_UOPS",
+/* 57 */{.name = "RETIRED_UOPS",
.code = 0xC1,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired uops",
},
-/* 56 */{.name = "RETIRED_BRANCH_INSTRUCTIONS",
+/* 58 */{.name = "RETIRED_BRANCH_INSTRUCTIONS",
.code = 0xC2,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Branch Instructions",
},
-/* 57 */{.name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
+/* 59 */{.name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
.code = 0xC3,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Mispredicted Branch Instructions",
},
-/* 58 */{.name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
+/* 60 */{.name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
.code = 0xC4,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Taken Branch Instructions",
},
-/* 59 */{.name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
+/* 61 */{.name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
.code = 0xC5,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Taken Branch Instructions Mispredicted",
},
-/* 60 */{.name = "RETIRED_FAR_CONTROL_TRANSFERS",
+/* 62 */{.name = "RETIRED_FAR_CONTROL_TRANSFERS",
.code = 0xC6,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Far Control Transfers",
},
-/* 61 */{.name = "RETIRED_BRANCH_RESYNCS",
+/* 63 */{.name = "RETIRED_BRANCH_RESYNCS",
.code = 0xC7,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Branch Resyncs",
},
-/* 62 */{.name = "RETIRED_NEAR_RETURNS",
+/* 64 */{.name = "RETIRED_NEAR_RETURNS",
.code = 0xC8,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Near Returns",
},
-/* 63 */{.name = "RETIRED_NEAR_RETURNS_MISPREDICTED",
+/* 65 */{.name = "RETIRED_NEAR_RETURNS_MISPREDICTED",
.code = 0xC9,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Near Returns Mispredicted",
},
-/* 64 */{.name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
+/* 66 */{.name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
.code = 0xCA,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Indirect Branches Mispredicted",
},
-/* 65 */{.name = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
+/* 67 */{.name = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
.code = 0xCB,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired MMX/FP Instructions",
@@ -1018,7 +1119,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 66 */{.name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS",
+/* 68 */{.name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS",
.code = 0xCC,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired Fastpath Double Op Instructions",
@@ -1043,77 +1144,77 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 67 */{.name = "INTERRUPTS_MASKED_CYCLES",
+/* 69 */{.name = "INTERRUPTS_MASKED_CYCLES",
.code = 0xCD,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Interrupts-Masked Cycles",
},
-/* 68 */{.name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
+/* 70 */{.name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
.code = 0xCE,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Interrupts-Masked Cycles with Interrupt Pending",
},
-/* 69 */{.name = "INTERRUPTS_TAKEN",
+/* 71 */{.name = "INTERRUPTS_TAKEN",
.code = 0xCF,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Interrupts Taken",
},
-/* 70 */{.name = "DECODER_EMPTY",
+/* 72 */{.name = "DECODER_EMPTY",
.code = 0xD0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Decoder Empty",
},
-/* 71 */{.name = "DISPATCH_STALLS",
+/* 73 */{.name = "DISPATCH_STALLS",
.code = 0xD1,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stalls",
},
-/* 72 */{.name = "DISPATCH_STALL_FOR_BRANCH_ABORT",
+/* 74 */{.name = "DISPATCH_STALL_FOR_BRANCH_ABORT",
.code = 0xD2,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for Branch Abort to Retire",
},
-/* 73 */{.name = "DISPATCH_STALL_FOR_SERIALIZATION",
+/* 75 */{.name = "DISPATCH_STALL_FOR_SERIALIZATION",
.code = 0xD3,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for Serialization",
},
-/* 74 */{.name = "DISPATCH_STALL_FOR_SEGMENT_LOAD",
+/* 76 */{.name = "DISPATCH_STALL_FOR_SEGMENT_LOAD",
.code = 0xD4,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for Segment Load",
},
-/* 75 */{.name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL",
+/* 77 */{.name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL",
.code = 0xD5,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for Reorder Buffer Full",
},
-/* 76 */{.name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL",
+/* 78 */{.name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL",
.code = 0xD6,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for Reservation Station Full",
},
-/* 77 */{.name = "DISPATCH_STALL_FOR_FPU_FULL",
+/* 79 */{.name = "DISPATCH_STALL_FOR_FPU_FULL",
.code = 0xD7,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for FPU Full",
},
-/* 78 */{.name = "DISPATCH_STALL_FOR_LS_FULL",
+/* 80 */{.name = "DISPATCH_STALL_FOR_LS_FULL",
.code = 0xD8,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for LS Full",
},
-/* 79 */{.name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET",
+/* 81 */{.name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET",
.code = 0xD9,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall Waiting for All Quiet",
},
-/* 80 */{.name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC",
+/* 82 */{.name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC",
.code = 0xDA,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Dispatch Stall for Far Transfer or Resync to Retire",
},
-/* 81 */{.name = "FPU_EXCEPTIONS",
+/* 83 */{.name = "FPU_EXCEPTIONS",
.code = 0xDB,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "FPU Exceptions",
@@ -1142,27 +1243,27 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 82 */{.name = "DR0_BREAKPOINT_MATCHES",
+/* 84 */{.name = "DR0_BREAKPOINT_MATCHES",
.code = 0xDC,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "DR0 Breakpoint Matches",
},
-/* 83 */{.name = "DR1_BREAKPOINT_MATCHES",
+/* 85 */{.name = "DR1_BREAKPOINT_MATCHES",
.code = 0xDD,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "DR1 Breakpoint Matches",
},
-/* 84 */{.name = "DR2_BREAKPOINT_MATCHES",
+/* 86 */{.name = "DR2_BREAKPOINT_MATCHES",
.code = 0xDE,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "DR2 Breakpoint Matches",
},
-/* 85 */{.name = "DR3_BREAKPOINT_MATCHES",
+/* 87 */{.name = "DR3_BREAKPOINT_MATCHES",
.code = 0xDF,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "DR3 Breakpoint Matches",
},
-/* 86 */{.name = "DRAM_ACCESSES_PAGE",
+/* 88 */{.name = "DRAM_ACCESSES_PAGE",
.code = 0xE0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "DRAM Accesses",
@@ -1199,7 +1300,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 87 */{.name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS",
+/* 89 */{.name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS",
.code = 0xE1,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "DRAM Controller Page Table Overflows",
@@ -1220,7 +1321,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 88 */{.name = "MEMORY_CONTROLLER_SLOT_MISSES",
+/* 90 */{.name = "MEMORY_CONTROLLER_SLOT_MISSES",
.code = 0xE2,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Memory Controller DRAM Command Slots Missed",
@@ -1241,7 +1342,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 89 */{.name = "MEMORY_CONTROLLER_TURNAROUNDS",
+/* 91 */{.name = "MEMORY_CONTROLLER_TURNAROUNDS",
.code = 0xE3,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Memory Controller Turnarounds",
@@ -1278,7 +1379,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 90 */{.name = "MEMORY_CONTROLLER_BYPASS",
+/* 92 */{.name = "MEMORY_CONTROLLER_BYPASS",
.code = 0xE4,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Memory Controller Bypass Counter Saturation",
@@ -1307,7 +1408,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 91 */{.name = "THERMAL_STATUS_AND_ECC_ERRORS",
+/* 93 */{.name = "THERMAL_STATUS_AND_ECC_ERRORS",
.code = 0xE8,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Thermal Status",
@@ -1340,7 +1441,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 92 */{.name = "CPU_IO_REQUESTS_TO_MEMORY_IO",
+/* 94 */{.name = "CPU_IO_REQUESTS_TO_MEMORY_IO",
.code = 0xE9,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU/IO Requests to Memory/IO",
@@ -1385,7 +1486,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 93 */{.name = "CACHE_BLOCK",
+/* 95 */{.name = "CACHE_BLOCK",
.code = 0xEA,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Cache Block Commands",
@@ -1418,7 +1519,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 94 */{.name = "SIZED_COMMANDS",
+/* 96 */{.name = "SIZED_COMMANDS",
.code = 0xEB,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Sized Commands",
@@ -1433,7 +1534,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
.ucode = 0x02,
},
{ .uname = "POSTED_WRITE_BYTE",
- .udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA
writes, size varies; also flushes of partially-filled Write Combining buffer",
+ .udesc = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA
writes, size varies; also flushes of partially-filled Write Combining buffer",
.ucode = 0x04,
},
{ .uname = "POSTED_WRITE_DWORD",
@@ -1455,7 +1556,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 95 */{.name = "PROBE",
+/* 97 */{.name = "PROBE",
.code = 0xEC,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Probe Responses and Upstream Requests",
@@ -1500,7 +1601,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 96 */{.name = "GART",
+/* 98 */{.name = "GART",
.code = 0xEE,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "GART Events",
@@ -1545,7 +1646,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 97 */{.name = "MEMORY_CONTROLLER_REQUESTS",
+/* 99 */{.name = "MEMORY_CONTROLLER_REQUESTS",
.code = 0x1F0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Memory Controller Requests",
@@ -1590,7 +1691,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 98 */{.name = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE",
+/* 100 */{.name = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE",
.code = 0x1E0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU to DRAM Requests to Target Node",
@@ -1635,7 +1736,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 99 */{.name = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE",
+/* 101 */{.name = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE",
.code = 0x1E1,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "IO to DRAM Requests to Target Node",
@@ -1680,7 +1781,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 100 */{.name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3",
+/* 102 */{.name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3",
.code = 0x1E2,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU Read Command Latency to Target Node 0-3",
@@ -1725,7 +1826,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 101 */{.name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3",
+/* 103 */{.name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3",
.code = 0x1E3,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU Read Command Requests to Target Node 0-3",
@@ -1770,7 +1871,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 102 */{.name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7",
+/* 104 */{.name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7",
.code = 0x1E4,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU Read Command Latency to Target Node 4-7",
@@ -1815,7 +1916,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 103 */{.name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7",
+/* 105 */{.name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7",
.code = 0x1E5,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU Read Command Requests to Target Node 4-7",
@@ -1860,7 +1961,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 104 */{.name = "CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7",
+/* 106 */{.name = "CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7",
.code = 0x1E6,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU Command Latency to Target Node 0-3/4-7",
@@ -1905,7 +2006,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 105 */{.name = "CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7",
+/* 107 */{.name = "CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7",
.code = 0x1E7,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "CPU Requests to Target Node 0-3/4-7",
@@ -1950,7 +2051,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 106 */{.name = "HYPERTRANSPORT_LINK0",
+/* 108 */{.name = "HYPERTRANSPORT_LINK0",
.code = 0xF6,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "HyperTransport Link 0 Transmit Bandwidth",
@@ -1991,7 +2092,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 107 */{.name = "HYPERTRANSPORT_LINK1",
+/* 109 */{.name = "HYPERTRANSPORT_LINK1",
.code = 0xF7,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "HyperTransport Link 1 Transmit Bandwidth",
@@ -2032,7 +2133,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 108 */{.name = "HYPERTRANSPORT_LINK2",
+/* 110 */{.name = "HYPERTRANSPORT_LINK2",
.code = 0xF8,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "HyperTransport Link 2 Transmit Bandwidth",
@@ -2073,7 +2174,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 109 */{.name = "HYPERTRANSPORT_LINK3",
+/* 111 */{.name = "HYPERTRANSPORT_LINK3",
.code = 0x1F9,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "HyperTransport Link 3 Transmit Bandwidth",
@@ -2114,7 +2215,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 110 */{.name = "READ_REQUEST_TO_L3_CACHE",
+/* 112 */{.name = "READ_REQUEST_TO_L3_CACHE",
.code = 0x4E0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Read Request to L3 Cache",
@@ -2156,7 +2257,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 111 */{.name = "L3_CACHE_MISSES",
+/* 113 */{.name = "L3_CACHE_MISSES",
.code = 0x4E1,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L3 Cache Misses",
@@ -2198,7 +2299,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 112 */{.name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
+/* 114 */{.name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
.code = 0x4E2,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L3 Fills caused by L2 Evictions",
@@ -2244,7 +2345,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 113 */{.name = "L3_EVICTIONS",
+/* 115 */{.name = "L3_EVICTIONS",
.code = 0x4E3,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L3 Evictions",
@@ -2276,7 +2377,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
/* Family 10h RevC, Shanghai */
-/* 114 */{.name = "PAGE_SIZE_MISMATCHES",
+/* 116 */{.name = "PAGE_SIZE_MISMATCHES",
.code = 0x165,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Page Size Mismatches",
@@ -2302,7 +2403,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 115 */{.name = "RETIRED_X87_OPS",
+/* 117 */{.name = "RETIRED_X87_OPS",
.code = 0x1C0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Retired x87 Floating Point Operations",
@@ -2328,25 +2429,25 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 116 */{.name = "IBS_OPS_TAGGED",
+/* 118 */{.name = "IBS_OPS_TAGGED",
.code = 0x1CF,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "IBS Ops Tagged",
.flags = AMD64_FL_FAM10H_REV_C,
},
-/* 117 */{.name = "LFENCE_INST_RETIRED",
+/* 119 */{.name = "LFENCE_INST_RETIRED",
.code = 0x1D3,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "LFENCE Instructions Retired",
.flags = AMD64_FL_FAM10H_REV_C,
},
-/* 118 */{.name = "SFENCE_INST_RETIRED",
+/* 120 */{.name = "SFENCE_INST_RETIRED",
.code = 0x1D4,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "SFENCE Instructions Retired",
.flags = AMD64_FL_FAM10H_REV_C,
},
-/* 119 */{.name = "MFENCE_INST_RETIRED",
+/* 121 */{.name = "MFENCE_INST_RETIRED",
.code = 0x1D5,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "MFENCE Instructions Retired",
@@ -2355,7 +2456,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
/* Family 10h RevD, Istanbul */
-/* 120 */{.name = "READ_REQUEST_TO_L3_CACHE",
+/* 122 */{.name = "READ_REQUEST_TO_L3_CACHE",
.code = 0x4E0,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "Read Request to L3 Cache",
@@ -2409,7 +2510,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 121 */{.name = "L3_CACHE_MISSES",
+/* 123 */{.name = "L3_CACHE_MISSES",
.code = 0x4E1,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L3 Cache Misses",
@@ -2463,7 +2564,7 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 122 */{.name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
+/* 124 */{.name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
.code = 0x4E2,
.modmsk = AMD64_FAM10H_ATTRS,
.desc = "L3 Fills caused by L2 Evictions",
@@ -2521,19 +2622,75 @@ static const amd64_entry_t amd64_fam10h_pe[]={
},
},
},
-/* 123 */{.name = "IBSFETCH_EVENT",
- .code = 0xff,
+/* 125 */{.name = "NON_CANCELLED_L3_READ_REQUESTS",
+ .code = 0x4ED,
+ .modmsk = AMD64_FAM10H_ATTRS,
+ .desc = "Non-cancelled L3 Read Requests",
+ .flags = AMD64_FL_FAM10H_REV_D,
+ .numasks = 11,
+ .umasks = {
+ { .uname = "READ_BLOCK_EXCLUSIVE",
+ .udesc = "Read Block Exclusive (Data cache read)",
+ .ucode = 0x01,
+ },
+ { .uname = "READ_BLOCK_SHARED",
+ .udesc = "Read Block Shared (Instruction cache read)",
+ .ucode = 0x02,
+ },
+ { .uname = "READ_BLOCK_MODIFY",
+ .udesc = "Read Block Modify",
+ .ucode = 0x04,
+ },
+ { .uname = "CORE_0_SELECT",
+ .udesc = "Core 0 Select",
+ .ucode = 0x00,
+ },
+ { .uname = "CORE_1_SELECT",
+ .udesc = "Core 1 Select",
+ .ucode = 0x10,
+ },
+ { .uname = "CORE_2_SELECT",
+ .udesc = "Core 2 Select",
+ .ucode = 0x20,
+ },
+ { .uname = "CORE_3_SELECT",
+ .udesc = "Core 3 Select",
+ .ucode = 0x30,
+ },
+ { .uname = "CORE_4_SELECT",
+ .udesc = "Core 4 Select",
+ .ucode = 0x40,
+ },
+ { .uname = "CORE_5_SELECT",
+ .udesc = "Core 5 Select",
+ .ucode = 0x50,
+ },
+ { .uname = "ANY_CORE",
+ .udesc = "Any core",
+ .ucode = 0xF0,
+ },
+ { .uname = "ALL",
+ .udesc = "All sub-events selected",
+ .ucode = 0xF7,
+ .uflags = AMD64_FL_DFL|AMD64_FL_NCOMBO,
+ },
+ },
+ },
+
+/* Family 10h, IBS pseudo-events */
+
+/* 126 */{.name = "IBSFETCH_EVENT",
+ .code = 0xFF,
.modmsk = AMD64_FAM10H_ATTRS_IBSFE,
.desc = "pseudo-event to enable IBS Fetch sampling",
.flags = AMD64_FL_IBSFE,
- },
-
-/* 124 */{.name = "IBSOP_EVENT",
- .code = 0xff,
+ },
+/* 127 */{.name = "IBSOP_EVENT",
+ .code = 0xFF,
.modmsk = AMD64_FAM10H_ATTRS_IBSOP,
.desc = "pseudo-event to enable IBS Op sampling",
.flags = AMD64_FL_IBSOP,
- },
+ },
};
#define PME_AMD64_FAM10H_EVENT_COUNT
(sizeof(amd64_fam10h_pe)/sizeof(amd64_entry_t))
--
1.7.1
--
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.rich...@amd.com
------------------------------------------------------------------------------
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