Hi, On Wed, Jul 14, 2010 at 1:16 PM, Zoltán Majó <zoltan.m...@inf.ethz.ch> wrote: > Hi Stephane, > > >> That is why I have the event commented out. You need to find a way >> to encode the event and then have the kernel decode and use the >> extra MSR. That is not there yet. I had planned to fix this but got >> caught up with other issues. Will try to get this fixed. > > I also need the OFFCORE_RESPONSE_0 set of events on the Intel Nehalem. > I've been using perfmon2 until now, but I'd like to transition to > perf_events + libpfm4 at some point of time. How soon do you expect the > support for OFFCORE_RESPONSE_0 to be added to perf_events? > Hopefully within a month. There is some complexity associated with RSP_0 and RSP_1. The extra MSR is shared between HT-threads, so you need some code to enforce mutual exclusion to guaranteed correctness.
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