Hi all, I am wondering if I can get continuous sampling about every L2$ access with PEBS on Xeon E5410 processor. PEBS feature records the value of general registers on sample points, so I can get the data address trace of L2$ access with disassembly.
The naive way is to set the L2$ access event overflow threshold to 1, and it failed as excepted. The strange thing is that I can get the PEBS buffer overflow signal, but there is 0 PEBS entries when I read the buffer header. Then I increase the counter overflow threshold to 2 and 5, and I can get some valid PEBS entries, but the total number (number of samples * 2 or 5) is much less than the real times of L2$ accesses (I counted it in another run). So is there someway to force the processor stop executing user-application after each L2$ access and record PEBS entry? Is there limitation on the PMU hardware with very small overflow threshold? Thanks. -- Di Xu ICT, CAS ------------------------------------------------------------------------------ This SF.net email is sponsored by Sprint What will you do first with EVO, the first 4G phone? Visit sprint.com/first -- http://p.sf.net/sfu/sprint-com-first _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
