Hi,

On Thu, Jul 29, 2010 at 2:56 AM, L F <my.linux.for...@gmail.com> wrote:
> Hi,
> I'm using the sampling capability of perfmon to record last level cache
> misses. I'm using commands such as the following:
> taskset -c 4 pfmon  --smpl-outfile=pfout.out  --long-smpl-periods=1
> --show-time -e l3_cache_misses:0x27 ./a.out
> The output file contains instruction pointer (IP) values related to the last
> level cache (LLC) misses. I'm interested in the actual addresses that miss
> at the LLC. I wonder if there is away to obtain such address traces. I've

You cannot get the data address by sampling on l3_cache_misses on an AMD
system. The instruction address is the interrupt instruction address not the
address of the instruction that caused the miss. It never is actually and that's
not specific to AMD.

> tried to obtain such traces using IBS (not within perfmon) on AMD machines,
> but the accuracy of the miss trace is too low.

Yes, to get the data address, you have to use IBS. I think the inaccuracy you
are alluding to relates to the fact that very samples are cache misses. With
IBS you have no control over which instruction gets samples. You have to
run for a longer period to capture enough representative samples. There is
nothing you can do about this. But when a cache miss is sampled, the information
captured in the IBS registers is correct.


> If there's no other way, is it possible to hack the perfmon code to record
> actual miss addresses instead of IPs? If yes, can anyone guide me into the

To do this you'd need to analyze the control and data flow graphs. I don't think
you want to do this in the kernel.

> right direction (for example telling me which files I need to look at in
> order to do this)
> I'm not really an expert in linux and perfmon, so the more explanations the
> better!

Your best chance is to use IBS on AMD.


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