On Mon, 13 Sep 2010, DRAM Ninjas wrote:
> Obviously this is a far cry from the 99.7% miss rate that I'm expecting. One
> explanation I could
> imagine is that the prefetcher is doing a good job of bringing in cache lines
> since everything is
> stride 1, but I'm wondering why these results would be different than the
> paper.
>
> Could someone help me understand what is going on here or if I'm doing
> something wrong?
Since you're running on a Core2 machine, it should be possible to disable
prefetching to see if that's the issue.
http://www.cs.utk.edu/~vweaver1/projects/prefetch-disable/
Though from my experience on modern x86 systems it's nearly impossible to
correlate measured cache results to "expected" results.
Vince
vweav...@eecs.utk.edu
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