On Tue, 2011-03-01 at 15:50 +0200, Stephane Eranian wrote:
> +static void intel_ds_init_pebs_constraints(void)
> +{
> + /*
> + * we only know hwo to deal with Family 6
> + */
> + if (boot_cpu_data.x86 != 6) {
> + x86_pmu.pebs = 0;
> + return;
> + }
> +
> + switch (boot_cpu_data.x86_model) {
> + case 14: /* 65 nm core solo/duo, "Yonah" */
> + /* do not have PEBS */
> + x86_pmu.pebs = 0;
> + break;
> +
> + case 15: /* original 65 nm celeron/pentium/core2/xeon,
> "Merom"/"Conroe" */
> + case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L"
> */
> + case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
> + case 29: /* six-core 45 nm xeon "Dunnington" */
> + x86_pmu.pebs_constraints = intel_core_pebs_events;
> + pr_cont("(Core2), ");
> + break;
> +
> + case 26: /* 45 nm nehalem, "Bloomfield" */
> + case 30: /* 45 nm nehalem, "Lynnfield" */
> + case 46: /* 45 nm nehalem-ex, "Beckton" */
> + x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
> + pr_cont("(Nehalem), ");
> + break;
> +
> + case 28: /* Atom */
> + x86_pmu.pebs_constraints = intel_atom_pebs_events;
> + pr_cont("(Atom), ");
> + break;
> +
> + case 37: /* 32 nm nehalem, "Clarkdale" */
> + case 44: /* 32 nm nehalem, "Gulftown" */
> + x86_pmu.pebs_constraints = intel_westmere_pebs_events;
> + pr_cont("(Westmere), ");
> + break;
> +
> + default:
> + printk(KERN_CONT "PEBS not yet supported for model %d,",
> + boot_cpu_data.x86_model);
> + x86_pmu.pebs = 0;
> + }
> +}
Right so you mentioned you had something like this, but could we please
use the one model switch in perf_event_intel.c and not replicate that,
otherwise its too easy to miss a model someplace.
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