* Stephane Eranian <eran...@google.com> wrote:
> On Wed, Mar 2, 2011 at 1:56 AM, Lin Ming <ming.m....@intel.com> wrote:
> > On Wed, 2011-03-02 at 04:20 +0800, Stephane Eranian wrote:
> >> This patch updates PEBS event constraints for Intel Atom, Nehalem,
> >> Westmere.
> >>
> >> This patch also reorganizes the PEBS format/constraint detection code. It
> >> is
> >> now based on processor model and not PEBS format. Two processors may use
> >> the
> >> same PEBS format without have the same list of PEBS events.
> >>
> >> In this second version, we simplified the initialization of the PEBS
> >> constraints
> >> by leveraging the existing switch() statement in perf_event_intel.c. We
> >> also
> >> renamed the constraint tables to be more consistent with regular
> >> constraints.
> >
> > Hi, Stephane
> >
> > Nice updates.
> > Wondering where did you get these PEBS event constraints? I didn't find
> > these in the latest manual.
> >
> Yeah, the manual is lacking some information. The other source of information
> is the PTU event files (whatif.intel.com).
Plus i suspect you have performed testing on affected CPUs as well?
If yes then i think we want to push these fixes via perf/urgent - they seem to
nicely round up the constraints.
Thanks,
Ingo
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