I can't run pfmon. Does I need recompile kernel? And I failed to update "kernel
patch" and "light kernel patch".
BTW: The os is el5, and kernel is 2.6.18.
------------------ Original ------------------
From: "perfmon2-devel-request"<perfmon2-devel-requ...@lists.sourceforge.net>;
Date: Wed, Mar 2, 2011 04:28 PM
To: "perfmon2-devel"<perfmon2-devel@lists.sourceforge.net>;
Subject: perfmon2-devel Digest, Vol 41, Issue 1
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Today's Topics:
1. Re: [PATCH] Uncore support (stephane eranian)
2. Re: Uncore events and exclude_hv (stephane eranian)
3. [PATCH] Uncore support (Arun Sharma)
4. Sandy Bridge graphics performance counters (Dan Upton)
5. Re: Sandy Bridge graphics performance counters (stephane eranian)
6. [PATCH] perf_events: update PEBS event constraints
(Stephane Eranian)
----------------------------------------------------------------------
Message: 1
Date: Sat, 26 Feb 2011 00:36:19 +0100
From: stephane eranian <eran...@googlemail.com>
Subject: Re: [perfmon2] [PATCH] Uncore support
To: Arun Sharma <asha...@fb.com>
Cc: a...@infradead.org, a...@firstfloor.org, ming.m....@intel.com,
perfmon2-devel@lists.sourceforge.net
Message-ID:
<AANLkTikOkhJONWSkgXOuH9WM6N9RXSjDhXRX07=um...@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
On Sat, Feb 26, 2011 at 12:23 AM, Arun Sharma <asha...@fb.com> wrote:
> This is for supporting uncore events.
>
> I tested this diff with Lin Ming's uncore patch against the kernel
> http://thread.gmane.org/gmane.linux.kernel/1071064
>
> diff --git a/include/perfmon/perf_event.h b/include/perfmon/perf_event.h
> index defc88e..de5691e 100644
> --- a/include/perfmon/perf_event.h
> +++ b/include/perfmon/perf_event.h
> @@ -29,6 +29,7 @@ enum perf_type_id {
> ? ? ? ?PERF_TYPE_HW_CACHE ? ? ? ? ? ? ?= 3,
> ? ? ? ?PERF_TYPE_RAW ? ? ? ? ? ? ? ? ? = 4,
> ? ? ? ?PERF_TYPE_BREAKPOINT ? ? ? ? ? ?= 5,
> + ? ? ? PERF_TYPE_UNCORE ? ? ? ? ? ? ? ?= 6,
> ? ? ? ?PERF_TYPE_MAX, ? ? ? ? ? ? ? ? ?/* non-ABI */
> ?};
>
> diff --git a/lib/pfmlib_intel_nhm_unc.c b/lib/pfmlib_intel_nhm_unc.c
> index 7fcdf28..1221190 100644
> --- a/lib/pfmlib_intel_nhm_unc.c
> +++ b/lib/pfmlib_intel_nhm_unc.c
> @@ -100,17 +100,23 @@ pfm_wsm_unc_detect(void *this)
> ? ? ? ?return PFM_SUCCESS;
> ?}
>
> +#ifdef __linux__
> +#include "pfmlib_perf_event_priv.h"
> ?static int
> ?intel_nhm_unc_perf_encode(void *this, pfmlib_event_desc_t *e)
> ?{
> -#if 0
> ? ? ? ?struct perf_event_attr *attr = e->os_data;
> - ? ? ? /* not yet supported by perf_event */
> - ? ? ? attr->type = PERF_TYPE_RAW;
> + ? ? ? attr->type = PERF_TYPE_UNCORE;
> ? ? ? ?attr->config = e->codes[0];
> -#endif
> - ? ? ? return PFM_ERR_NOTSUPP;
> + ? ? ? /* Can't exclude anything */
> + ? ? ? attr->exclude_user = 0;
> + ? ? ? attr->exclude_kernel = 0;
> + ? ? ? attr->exclude_hv = 0;
> + ? ? ? attr->exclude_idle = 0;
> +
> + ? ? ? return PFM_SUCCESS;
> ?}
> +#endif
>
> ?static int
> ?intel_nhm_unc_os_encode(void *this, pfmlib_event_desc_t *e)
> diff --git a/lib/pfmlib_perf_event.c b/lib/pfmlib_perf_event.c
> index 879efb6..1c7a90b 100644
> --- a/lib/pfmlib_perf_event.c
> +++ b/lib/pfmlib_perf_event.c
> @@ -83,6 +83,7 @@ pfmlib_perf_event_encode(void *this, const char *str, int
> dfl_plm, void *data)
>
> ? ? ? ?e.osid = os->id;
> ? ? ? ?e.os_data = attr;
> + ? ? ? e.dfl_plm = dfl_plm;
>
That bit could be passed but I think it is useless in most cases,
perf_event controls priv levels.
Now the one thing that I need to handle better is that for uncore-type
of PMU, dfl_plm better be
PLM0|PLM3. Otherwise, libpfm4 needs to return an error. I want
something explicit so that
people understand that uncore PMU ALWAYS monitor at both user +
kernel. Silent errors
are nasty, so I want to try and avoid that as much as possible.
> ? ? ? ?ret = pfmlib_parse_event(str, &e);
> ? ? ? ?if (ret != PFM_SUCCESS)
>
------------------------------
Message: 2
Date: Sat, 26 Feb 2011 00:37:16 +0100
From: stephane eranian <eran...@googlemail.com>
Subject: Re: [perfmon2] Uncore events and exclude_hv
To: Arun Sharma <asha...@fb.com>
Cc: a...@infradead.org, a...@firstfloor.org, ming.m....@intel.com,
perfmon2-devel@lists.sourceforge.net
Message-ID:
<AANLkTik1vqrb4LS2p6QuzOqXZWDhTr9m0=xN=uefp...@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
On Sat, Feb 26, 2011 at 12:34 AM, Arun Sharma <asha...@fb.com> wrote:
>
> I had to hack around one thing to make perf+libpfm4 work with uncore events:
>
> --- a/lib/pfmlib_perf_event.c
> +++ b/lib/pfmlib_perf_event.c
> @@ -153,7 +153,7 @@ pfmlib_perf_event_encode(void *this, const char *str, int
> dfl_plm, void *data)
>
> ? ? ? ?attr->exclude_user = !(plm & PFM_PLM3);
> ? ? ? ?attr->exclude_kernel = !(plm & PFM_PLM0);
> - ? ? ? attr->exclude_hv = !(plm & PFM_PLMH);
> + ? ? ? //attr->exclude_hv = !(plm & PFM_PLMH);
>
> The problem is that the kernel expects exclude_hv == 0, otherwise the
> perf_event_open syscall errors out. However, if I pass PFM_PLMH
> pfm_get_perf_event_encoding(), I get a different error.
>
> static int
> pfm_nhm_unc_get_encoding(void *this, pfmlib_event_desc_t *e)
> {
> ? ? ? ?...
> ? ? ? ?if (e->dfl_plm != (PFM_PLM0|PFM_PLM3)) {
> ? ? ? ? ? ? ? ?DPRINT("dfl_plm must be PLM0|PLM3 with Intel uncore PMU\n");
> ? ? ? ? ? ? ? ?return PFM_ERR_INVAL;
> ? ? ? ?}
> }
>
> Perhaps there is a better answer?
>
Yeah, I need to cleanup this part.
Need to think of a good way of handling this at the perf_event layer.
> ?-Arun
>
>
------------------------------
Message: 3
Date: Fri, 25 Feb 2011 15:23:20 -0800
From: Arun Sharma <asha...@fb.com>
Subject: [perfmon2] [PATCH] Uncore support
To: eran...@gmail.com
Cc: a...@infradead.org, a...@firstfloor.org, ming.m....@intel.com,
perfmon2-devel@lists.sourceforge.net
Message-ID: <20110225232320.ga2...@dev1756.snc6.facebook.com>
Content-Type: text/plain; charset=us-ascii
This is for supporting uncore events.
I tested this diff with Lin Ming's uncore patch against the kernel
http://thread.gmane.org/gmane.linux.kernel/1071064
diff --git a/include/perfmon/perf_event.h b/include/perfmon/perf_event.h
index defc88e..de5691e 100644
--- a/include/perfmon/perf_event.h
+++ b/include/perfmon/perf_event.h
@@ -29,6 +29,7 @@ enum perf_type_id {
PERF_TYPE_HW_CACHE = 3,
PERF_TYPE_RAW = 4,
PERF_TYPE_BREAKPOINT = 5,
+ PERF_TYPE_UNCORE = 6,
PERF_TYPE_MAX, /* non-ABI */
};
diff --git a/lib/pfmlib_intel_nhm_unc.c b/lib/pfmlib_intel_nhm_unc.c
index 7fcdf28..1221190 100644
--- a/lib/pfmlib_intel_nhm_unc.c
+++ b/lib/pfmlib_intel_nhm_unc.c
@@ -100,17 +100,23 @@ pfm_wsm_unc_detect(void *this)
return PFM_SUCCESS;
}
+#ifdef __linux__
+#include "pfmlib_perf_event_priv.h"
static int
intel_nhm_unc_perf_encode(void *this, pfmlib_event_desc_t *e)
{
-#if 0
struct perf_event_attr *attr = e->os_data;
- /* not yet supported by perf_event */
- attr->type = PERF_TYPE_RAW;
+ attr->type = PERF_TYPE_UNCORE;
attr->config = e->codes[0];
-#endif
- return PFM_ERR_NOTSUPP;
+ /* Can't exclude anything */
+ attr->exclude_user = 0;
+ attr->exclude_kernel = 0;
+ attr->exclude_hv = 0;
+ attr->exclude_idle = 0;
+
+ return PFM_SUCCESS;
}
+#endif
static int
intel_nhm_unc_os_encode(void *this, pfmlib_event_desc_t *e)
diff --git a/lib/pfmlib_perf_event.c b/lib/pfmlib_perf_event.c
index 879efb6..1c7a90b 100644
--- a/lib/pfmlib_perf_event.c
+++ b/lib/pfmlib_perf_event.c
@@ -83,6 +83,7 @@ pfmlib_perf_event_encode(void *this, const char *str, int
dfl_plm, void *data)
e.osid = os->id;
e.os_data = attr;
+ e.dfl_plm = dfl_plm;
ret = pfmlib_parse_event(str, &e);
if (ret != PFM_SUCCESS)
------------------------------
Message: 4
Date: Mon, 28 Feb 2011 11:06:20 -0500
From: Dan Upton <up...@virginia.edu>
Subject: [perfmon2] Sandy Bridge graphics performance counters
To: perfmon2-devel@lists.sourceforge.net
Message-ID:
<AANLkTi=V0FcuiN=+jbtaj4puht7not+viz4c_fpev...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
I haven't found anything about performance counters for the integrated
Intel HD graphics on Sandy Bridge, but maybe I'm looking in the wrong
place. Does anybody know if there are any publicly-exposed counters,
and if so, are they supported/will they be supported by libpfm4?
Thanks,
-dan
------------------------------
Message: 5
Date: Mon, 28 Feb 2011 17:13:32 +0100
From: stephane eranian <eran...@googlemail.com>
Subject: Re: [perfmon2] Sandy Bridge graphics performance counters
To: Dan Upton <up...@virginia.edu>
Cc: perfmon2-devel@lists.sourceforge.net
Message-ID:
<AANLkTimpN3c0M9opQD9Q2B=gannus_mv3zgp48f2u...@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Hi Dan,
On Mon, Feb 28, 2011 at 5:06 PM, Dan Upton <up...@virginia.edu> wrote:
> I haven't found anything about performance counters for the integrated
> Intel HD graphics on Sandy Bridge, but maybe I'm looking in the wrong
> place. ?Does anybody know if there are any publicly-exposed counters,
> and if so, are they supported/will they be supported by libpfm4?
>
I have not seen anything so far.
If they exists, those counters would first need perf_event support.
We could certainly add the table to libpfm4 after that.
------------------------------
Message: 6
Date: Tue, 1 Mar 2011 15:50:01 +0200
From: Stephane Eranian <eran...@google.com>
Subject: [perfmon2] [PATCH] perf_events: update PEBS event constraints
To: linux-ker...@vger.kernel.org
Cc: perfmon2-de...@lists.sf.net, ming.m....@intel.com,
pet...@infradead.org, fweis...@gmail.com, eran...@google.com,
a...@redhat.com, pau...@samba.org, mi...@elte.hu, da...@davemloft.net,
eran...@gmail.com
Message-ID: <4d6d079f.9104df0a.5a71.ffffd...@mx.google.com>
This patch updates PEBS event constraints for Intel Atom, Nehalem, Westmere.
This patch also reorganizes the PEBS format/constraint detection code. It is
now based on processor model and not PEBS format. Two processors may use the
same PEBS format without have the same list of PEBS events.
Signed-off-by: Stephane Eranian <eran...@google.com>
---
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c
b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index b7dcd9f..9b7ca73 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -361,30 +361,49 @@ static int intel_pmu_drain_bts_buffer(void)
/*
* PEBS
*/
-
static struct event_constraint intel_core_pebs_events[] = {
PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
- PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
- PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
- PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
- PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
- PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
+ INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
+ EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_atom_pebs_events[] = {
+ PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
+ PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
+ PEBS_EVENT_CONSTRAINT(0x0ac4, 0x1), /* BR_INST_RETIRED.MISPRED */
+ INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
EVENT_CONSTRAINT_END
};
static struct event_constraint intel_nehalem_pebs_events[] = {
- PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
- PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
- PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
- PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
- PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
- PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
- PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
- PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
- PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
+ INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
+ PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+ INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
+ INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0x00c4, 0xf),/* BR_INST_RETIRED.* */
+ PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
+ INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
+ PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+ INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
+ EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_westmere_pebs_events[] = {
+ INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
+ PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+ INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
+
+ INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
+ PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+ INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
EVENT_CONSTRAINT_END
};
@@ -676,6 +695,55 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
* BTS, PEBS probe and setup
*/
+static void intel_ds_init_pebs_constraints(void)
+{
+ /*
+ * we only know hwo to deal with Family 6
+ */
+ if (boot_cpu_data.x86 != 6) {
+ x86_pmu.pebs = 0;
+ return;
+ }
+
+ switch (boot_cpu_data.x86_model) {
+ case 14: /* 65 nm core solo/duo, "Yonah" */
+ /* do not have PEBS */
+ x86_pmu.pebs = 0;
+ break;
+
+ case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
+ case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
+ case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
+ case 29: /* six-core 45 nm xeon "Dunnington" */
+ x86_pmu.pebs_constraints = intel_core_pebs_events;
+ pr_cont("(Core2), ");
+ break;
+
+ case 26: /* 45 nm nehalem, "Bloomfield" */
+ case 30: /* 45 nm nehalem, "Lynnfield" */
+ case 46: /* 45 nm nehalem-ex, "Beckton" */
+ x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
+ pr_cont("(Nehalem), ");
+ break;
+
+ case 28: /* Atom */
+ x86_pmu.pebs_constraints = intel_atom_pebs_events;
+ pr_cont("(Atom), ");
+ break;
+
+ case 37: /* 32 nm nehalem, "Clarkdale" */
+ case 44: /* 32 nm nehalem, "Gulftown" */
+ x86_pmu.pebs_constraints = intel_westmere_pebs_events;
+ pr_cont("(Westmere), ");
+ break;
+
+ default:
+ printk(KERN_CONT "PEBS not yet supported for model %d,",
+ boot_cpu_data.x86_model);
+ x86_pmu.pebs = 0;
+ }
+}
+
static void intel_ds_init(void)
{
/*
@@ -692,24 +760,24 @@ static void intel_ds_init(void)
switch (format) {
case 0:
- printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
+ printk(KERN_CONT "PEBS fmt0%c ", pebs_type);
x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
- x86_pmu.pebs_constraints = intel_core_pebs_events;
break;
case 1:
- printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
+ printk(KERN_CONT "PEBS fmt1%c ", pebs_type);
x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
- x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
break;
default:
- printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
+ printk(KERN_CONT "no PEBS fmt%d%c\n",
+ format, pebs_type);
x86_pmu.pebs = 0;
- break;
+ return;
}
+ intel_ds_init_pebs_constraints();
}
}
------------------------------
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