Hi, sorry in advance if I put this in the wrong place.
I need to capture all data accesses to L2 shared cache and misses in the L2 cache of the target process. To capture L2 cache references between misses, I use `pfmon -eLAST_LEVEL_CACHE_MISSES, LAST_LEVEL_CACHE_REFERENCES --long-smpl-periods=1 --reset -- ./prog`. But I am not quite sure about the following three questions. 1) I know that LAST_LEVEL_CACHE_REFERENCES event include L1 instruction and data cache misses, BUT Do accesses to L2 cache include L1 data write-through accesses and hardware prefetches? 2) Due to multiple instruction issue and out-of-order execution, there may be more than one L1 data cache misses being serviced in parallel by the two load-store units of the processor. Under such circumstance, Will the two misses cause two miss events OR just one miss event, and the two misses will be counted as two references in L2??? 3) Raising an exception on each LAST_LEVEL_CACHE_MISSES=1 event is costy. Does exist HW support on my Xeon E5310 that automatically records LAST_LEVEL_CACHE_REFERENCES when LAST_LEVEL_CACHE_MISSES=1 into a small pre-designed buffer, either within the process core or in main memory, raising an exception only when the buffer overflows so that the cost of overflow exception is lower??? Thanks in advance. ------------------------------------------------------------------------------ Benefiting from Server Virtualization: Beyond Initial Workload Consolidation -- Increasing the use of server virtualization is a top priority.Virtualization can reduce costs, simplify management, and improve application availability and disaster protection. Learn more about boosting the value of server virtualization. http://p.sf.net/sfu/vmware-sfdev2dev _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
