Updated event table for AMD Family 15h cpus from:
Apr 29 2011 -- Robert Richter, robert.rich...@amd.com:
Source: BKDG for AMD Family 15h Models 00h-0Fh Processors,
42301, Rev 1.15, April 18, 2011
These events have been added for family 15h:
PMCx029 LS Dispatch
PMCx030 Executed CLFLUSH Instructions
PMCx16C L2 Prefetcher Trigger Events
PMCx1D8 Dispatch Stall for STQ Full
NBPMCx1EA Request Cache Status 0
NBPMCx1EB Request Cache Status 1
NBPMCx4EF L3 Latency
Signed-off-by: Robert Richter <robert.rich...@amd.com>
---
lib/amd64_events_fam15h.h | 187 ++++++++++++++++++++++++++++++++++++++++++---
1 files changed, 177 insertions(+), 10 deletions(-)
diff --git a/lib/amd64_events_fam15h.h b/lib/amd64_events_fam15h.h
index 8ecf6d9..672f108 100644
--- a/lib/amd64_events_fam15h.h
+++ b/lib/amd64_events_fam15h.h
@@ -23,12 +23,16 @@
* applications on Linux.
*/
-/* History
+/*
+ * Family 15h Microarchitecture performance monitor events
*
- * Dec 09 2010 -- Robert Richter, robert.rich...@amd.com:
+ * History:
*
- * Family 15h Microarchitecture performance monitor events
+ * Apr 29 2011 -- Robert Richter, robert.rich...@amd.com:
+ * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors,
+ * 42301, Rev 1.15, April 18, 2011
*
+ * Dec 09 2010 -- Robert Richter, robert.rich...@amd.com:
* Source: BIOS and Kernel Developer's Guide for the AMD Family 15h
* Processors, Rev 0.90, May 18, 2010
*/
@@ -268,11 +272,11 @@ static pme_amd64_entry_t amd64_fam15h_pe[]={
.pme_ucode = 1 << 0,
},
{ .pme_uname = "CYCLES_NON_SPECULATIVE_PHASE",
- .pme_udesc = "Number of cycles spent non-speculative phase
(including cache miss penalty)",
+ .pme_udesc = "Number of cycles spent in non-speculative
phase, excluding cache miss penalty",
.pme_ucode = 1 << 2,
},
{ .pme_uname = "CYCLES_WAITING",
- .pme_udesc = "Number of cycles waiting for a cache hit (cache
miss penalty)",
+ .pme_udesc = "Number of cycles spent in non-speculative
phase, including the cache miss penalty",
.pme_ucode = 1 << 3,
},
{ .pme_uname = "ALL",
@@ -472,12 +476,12 @@ static pme_amd64_entry_t amd64_fam15h_pe[]={
.pme_numasks = 3,
.pme_umasks = {
{ .pme_uname = "SW_PREFETCH_HIT_IN_L1",
- .pme_udesc = "Software prefetch hit in the L1.",
- .pme_ucode = 0x01,
+ .pme_udesc = "Software prefetch hit in the L1",
+ .pme_ucode = 1 << 0,
},
{ .pme_uname = "SW_PREFETCH_HIT_IN_L2",
- .pme_udesc = "Software prefetch hit in L2.",
- .pme_ucode = 0x08,
+ .pme_udesc = "Software prefetch hit in the L2",
+ .pme_ucode = 1 << 3,
},
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
@@ -1056,7 +1060,7 @@ static pme_amd64_entry_t amd64_fam15h_pe[]={
.pme_ucode = 1 << 1,
},
{ .pme_uname = "IGNORED",
- .pme_udesc = "Number of times op could not be tagged due to
other tagged op active in pipe",
+ .pme_udesc = "Number of times an op could not be tagged by
IBS because of a previous tagged op that has not retired",
.pme_ucode = 1 << 2,
},
{ .pme_uname = "ALL",
@@ -2244,6 +2248,169 @@ static pme_amd64_entry_t amd64_fam15h_pe[]={
},
},
#endif
+/* 107 */{.pme_name = "LS_DISPATCH",
+ .pme_code = 0x29,
+ .pme_desc = "LS Dispatch",
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
+ .pme_numasks = 4,
+ .pme_umasks = {
+ { .pme_uname = "LOADS",
+ .pme_udesc = "Loads",
+ .pme_ucode = 1 << 0,
+ },
+ { .pme_uname = "STORES",
+ .pme_udesc = "Stores",
+ .pme_ucode = 1 << 1,
+ },
+ { .pme_uname = "LOAD_OP_STORES",
+ .pme_udesc = "Load-op-Stores",
+ .pme_ucode = 1 << 2,
+ },
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x07,
+ },
+ },
+ },
+/* 108 */{.pme_name = "EXECUTED_CLFLUSH_INSTRUCTIONS",
+ .pme_code = 0x30,
+ .pme_desc = "Executed CLFLUSH Instructions",
+ },
+/* 109 */{.pme_name = "L2_PREFETCHER_TRIGGER_EVENTS",
+ .pme_code = 0x16C,
+ .pme_desc = "L2 Prefetcher Trigger Events",
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
+ .pme_numasks = 3,
+ .pme_umasks = {
+ { .pme_uname = "LOAD_L1_MISS_SEEN_BY_PREFETCHER",
+ .pme_udesc = "Load L1 miss seen by prefetcher",
+ .pme_ucode = 1 << 0,
+ },
+ { .pme_uname = "STORE_L1_MISS_SEEN_BY_PREFETCHER",
+ .pme_udesc = "Store L1 miss seen by prefetcher",
+ .pme_ucode = 1 << 1,
+ },
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x03,
+ },
+ },
+ },
+/* 110 */{.pme_name = "DISPATCH_STALL_FOR_STQ_FULL",
+ .pme_code = 0x1D8,
+ .pme_desc = "Dispatch Stall for STQ Full",
+ },
+/* Northbridge events (.pme_code & 0x0E0) not yet supported by the kernel */
+#if 0
+/* 111 */{.pme_name = "REQUEST_CACHE_STATUS_0",
+ .pme_code = 0x1EA,
+ .pme_desc = "Request Cache Status 0",
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
+ .pme_numasks = 9,
+ .pme_umasks = {
+ { .pme_uname = "PROBE_HIT_S",
+ .pme_udesc = "Probe Hit S",
+ .pme_ucode = 1 << 0,
+ },
+ { .pme_uname = "PROBE_HIT_E",
+ .pme_udesc = "Probe Hit E",
+ .pme_ucode = 1 << 1,
+ },
+ { .pme_uname = "PROBE_HIT_MUW_OR_O",
+ .pme_udesc = "Probe Hit MuW or O",
+ .pme_ucode = 1 << 2,
+ },
+ { .pme_uname = "PROBE_HIT_M",
+ .pme_udesc = "Probe Hit M",
+ .pme_ucode = 1 << 3,
+ },
+ { .pme_uname = "PROBE_MISS",
+ .pme_udesc = "Probe Miss",
+ .pme_ucode = 1 << 4,
+ },
+ { .pme_uname = "DIRECTED_PROBE",
+ .pme_udesc = "Directed Probe",
+ .pme_ucode = 1 << 5,
+ },
+ { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLK",
+ .pme_udesc = "Track Cache Stat for RdBlk",
+ .pme_ucode = 1 << 6,
+ },
+ { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLKS",
+ .pme_udesc = "Track Cache Stat for RdBlkS",
+ .pme_ucode = 1 << 7,
+ },
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0xFF,
+ },
+ },
+ },
+/* 112 */{.pme_name = "REQUEST_CACHE_STATUS_1",
+ .pme_code = 0x1EB,
+ .pme_desc = "Request Cache Status 1",
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
+ .pme_numasks = 9,
+ .pme_umasks = {
+ { .pme_uname = "PROBE_HIT_S",
+ .pme_udesc = "Probe Hit S",
+ .pme_ucode = 1 << 0,
+ },
+ { .pme_uname = "PROBE_HIT_E",
+ .pme_udesc = "Probe Hit E",
+ .pme_ucode = 1 << 1,
+ },
+ { .pme_uname = "PROBE_HIT_MUW_OR_O",
+ .pme_udesc = "Probe Hit MuW or O",
+ .pme_ucode = 1 << 2,
+ },
+ { .pme_uname = "PROBE_HIT_M",
+ .pme_udesc = "Probe Hit M",
+ .pme_ucode = 1 << 3,
+ },
+ { .pme_uname = "PROBE_MISS",
+ .pme_udesc = "Probe Miss",
+ .pme_ucode = 1 << 4,
+ },
+ { .pme_uname = "DIRECTED_PROBE",
+ .pme_udesc = "Directed Probe",
+ .pme_ucode = 1 << 5,
+ },
+ { .pme_uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY",
+ .pme_udesc = "Track Cache Stat for ChgToDirty",
+ .pme_ucode = 1 << 6,
+ },
+ { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLKM",
+ .pme_udesc = "Track Cache Stat for RdBlkM",
+ .pme_ucode = 1 << 7,
+ },
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0xFF,
+ },
+ },
+ },
+/* 113 */{.pme_name = "L3_LATENCY",
+ .pme_code = 0x4EF,
+ .pme_desc = "L3 Latency",
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
+ .pme_numasks = 3,
+ .pme_umasks = {
+ { .pme_uname = "L3CYCCOUNT",
+ .pme_udesc = "L3CycCount. L3 Request cycle count",
+ .pme_ucode = 1 << 0,
+ },
+ { .pme_uname = "L3REQCOUNT",
+ .pme_udesc = "L3ReqCount. L3 request count",
+ .pme_ucode = 1 << 1,
+ },
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x03,
+ },
+ },
+ },
+#endif
};
#define PME_AMD64_FAM15H_EVENT_COUNT
(sizeof(amd64_fam15h_pe)/sizeof(pme_amd64_entry_t))
--
1.7.3.4
------------------------------------------------------------------------------
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