On Wed, Jan 15, 2014 at 10:14 PM, Stephen Boyd <sb...@codeaurora.org> wrote:
> On 01/15, Vince Weaver wrote:
>>
>> diff --git a/lib/pfmlib_arm_armv7_pmuv1.c b/lib/pfmlib_arm_armv7_pmuv1.c
>> index 943101a..ccfb2ca 100644
>> --- a/lib/pfmlib_arm_armv7_pmuv1.c
>> +++ b/lib/pfmlib_arm_armv7_pmuv1.c
>> @@ -88,6 +89,25 @@ pfm_arm_detect_cortex_a15(void *this)
>> return PFM_ERR_NOTSUPP;
>> }
>>
>> +static int
>> +pfm_arm_detect_krait(void *this)
>> +{
>> +
>> + int ret;
>> +
>> + ret = pfm_arm_detect(this);
>> + if (ret != PFM_SUCCESS)
>> + return PFM_ERR_NOTSUPP;
>> +
>> + if (pfm_arm_cfg.implementer == 0x51) { /* Qualcomm */
>> + /* all chips are supported? */
>> + /* at least pfm_arm_cfg.part 0x04X and 0x06X are */
>> + return PFM_SUCCESS;
>
> We should check for midr[15:10] == 0x1 here too, so that we know
> we're running on a Krait CPU. Otherwise this check is also
> finding Scorpion CPUs.
>
>> + }
>> + return PFM_ERR_NOTSUPP;
>> +}
>> +
>> +
>> /* Cortex A8 support */
>> pfmlib_pmu_t arm_cortex_a8_support={
>> .desc = "ARM Cortex A8",
>> @@ -163,3 +183,29 @@ pfmlib_pmu_t arm_cortex_a15_support={
>> PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs),
>> .get_event_nattrs = pfm_arm_get_event_nattrs,
>> };
>> +
>> +/* Qualcomm Krait support */
>> +pfmlib_pmu_t arm_qcom_krait_support={
>> + .desc = "ARM Qualcomm Krait",
>> + .name = "qcom_krait",
>> + .pmu = PFM_PMU_ARM_QCOM_KRAIT,
>> + .pme_count = LIBPFM_ARRAY_SIZE(arm_qcom_krait_pe),
>> + .type = PFM_PMU_TYPE_CORE,
>> + .pe = arm_qcom_krait_pe,
>> +
>> + .pmu_detect = pfm_arm_detect_krait,
>> + .max_encoding = 1,
>> + .num_cntrs = 2,
>
> If this is the number of counters the CPU supports then it should
> say 5. At least, that is what gets printed on my devices.
>
> hw perfevents: enabled with ARMv7 Krait PMU driver, 5 counters available
>
It is the number of counters. This is informational and not used for the
perf_event support.
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