On Mon, Aug 31, 2015 at 7:20 AM, Qiong Cai <qiong....@gmail.com> wrote:
> Hi, > > What's the event format for events with threshold? The normal one is > something like > wsm_dp::DTLB_LOAD_MISSES:ANY. What's for > wsm_dp::MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD > ? > > Look at examples/showevtinfo wsm_dp:: PMU name : wsm_dp (Intel Westmere DP) Name : MEM_INST_RETIRED Equiv : None Flags : [precise] Desc : Memory instructions retired (Precise Event) Code : 0xb Umask-00 : 0x10 : PMU : [LATENCY_ABOVE_THRESHOLD] : [precise] : Memory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required) Umask-01 : 0x01 : PMU : [LOADS] : [precise] : Instructions retired which contains a load (Precise Event) Umask-02 : 0x02 : PMU : [STORES] : [precise] : Instructions retired which contains a store (Precise Event) Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean) Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean) Modif-02 : 0x02 : PMU : [e] : edge level (may require counter-mask >= 1) (boolean) Modif-03 : 0x03 : PMU : [i] : invert (boolean) Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer) Modif-05 : 0x05 : PMU : [t] : measure any thread (boolean) Modif-06 : 0x06 : PMU : [ldlat] : load latency threshold (cycles, [3-65535]) (integer) Use: wsm_dp::MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:ldlat=4 for instance > ThanksQiong > > > > > ------------------------------------------------------------------------------ > > _______________________________________________ > perfmon2-devel mailing list > perfmon2-devel@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/perfmon2-devel > >
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