On 01/29/2016 11:24 AM, William Cohen wrote:
> Some additional gcc warning flags have been turned on in Fedora rawhide and
> the warnings are causing the build of libpfm to fail. Below is an example of
> them. However, there are others that are not listed because the compile of
> those files wasn't attempted because the make exited early.
>
> -Will
>
> cc -g -Wall -Werror -Wextra -Wno-unused-parameter -I.
> -I/builddir/build/BUILD/libpfm-4.6.0/lib/../include -DCONFIG_PFMLIB_DEBUG
> -DCONFIG_PFMLIB_OS_LINUX -D_REENTRANT -I. -DCONFIG_PFMLIB_ARCH_X86
> -DCONFIG_PFMLIB_ARCH_I386 -I. -c pfmlib_intel_ivb_unc.c
> In file included from pfmlib_intel_snb_unc.c:31:0:
> events/intel_snb_unc_events.h:227:32: error: 'intel_snb_unc_arb_pe' defined
> but not used [-Werror=unused-const-variable]
> static const intel_x86_entry_t intel_snb_unc_arb_pe[]={
> ^~~~~~~~~~~~~~~~~~~~
> events/intel_snb_unc_events.h:145:32: error: 'snb_unc_arb_trk' defined but
> not used [-Werror=unused-const-variable]
> static const intel_x86_umask_t snb_unc_arb_trk[]={
> ^~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> /builddir/build/BUILD/libpfm-4.6.0/lib/../rules.mk:30: recipe for target
> 'pfmlib_intel_snb_unc.o' failed
> make[1]: *** [pfmlib_intel_snb_unc.o] Error 1
> make[1]: *** Waiting for unfinished jobs....
> In file included from pfmlib_intel_ivb_unc.c:31:0:
> events/intel_snb_unc_events.h:227:32: error: 'intel_snb_unc_arb_pe' defined
> but not used [-Werror=unused-const-variable]
> static const intel_x86_entry_t intel_snb_unc_arb_pe[]={
> ^~~~~~~~~~~~~~~~~~~~
> events/intel_snb_unc_events.h:145:32: error: 'snb_unc_arb_trk' defined but
> not used [-Werror=unused-const-variable]
> static const intel_x86_umask_t snb_unc_arb_trk[]={
> ^~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> /builddir/build/BUILD/libpfm-4.6.0/lib/../rules.mk:30: recipe for target
> 'pfmlib_intel_ivb_unc.o' failed
> make[1]: *** [pfmlib_intel_ivb_unc.o] Error 1
> make[1]: Leaving directory '/builddir/build/BUILD/libpfm-4.6.0/lib'
>
> ------------------------------------------------------------------------------
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>
As a first pass I went through and remove the unused initializers and the
attached patch shows what was remove to eliminate the unused const initializer
errors. This might not be the right approach, but it does list out the problem
initializers when building things on x86 machines. Some of the events and unit
masks might be supported by the processor and should remain.
-Will
diff --git a/lib/events/amd64_events_fam15h.h b/lib/events/amd64_events_fam15h.h
index 0b8c17b..4fdc10f 100644
--- a/lib/events/amd64_events_fam15h.h
+++ b/lib/events/amd64_events_fam15h.h
@@ -808,989 +808,6 @@ static const amd64_umask_t amd64_fam15h_l2_prefetcher_trigger_events[]={
},
};
-static const amd64_umask_t amd64_fam15h_dram_accesses[]={
- { .uname = "DCT0_PAGE_HIT",
- .udesc = "DCT0 Page hit",
- .ucode = 0x1,
- },
- { .uname = "DCT0_PAGE_MISS",
- .udesc = "DCT0 Page Miss",
- .ucode = 0x2,
- },
- { .uname = "DCT0_PAGE_CONFLICT",
- .udesc = "DCT0 Page Conflict",
- .ucode = 0x4,
- },
- { .uname = "DCT1_PAGE_HIT",
- .udesc = "DCT1 Page hit",
- .ucode = 0x8,
- },
- { .uname = "DCT1_PAGE_MISS",
- .udesc = "DCT1 Page Miss",
- .ucode = 0x10,
- },
- { .uname = "DCT1_PAGE_CONFLICT",
- .udesc = "DCT1 Page Conflict",
- .ucode = 0x20,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_dram_controller_page_table_overflows[]={
- { .uname = "DCT0_PAGE_TABLE_OVERFLOW",
- .udesc = "DCT0 Page Table Overflow",
- .ucode = 0x1,
- },
- { .uname = "DCT1_PAGE_TABLE_OVERFLOW",
- .udesc = "DCT1 Page Table Overflow",
- .ucode = 0x2,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3,
- .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_memory_controller_dram_command_slots_missed[]={
- { .uname = "DCT0_COMMAND_SLOTS_MISSED",
- .udesc = "DCT0 Command Slots Missed (in MemClks)",
- .ucode = 0x1,
- },
- { .uname = "DCT1_COMMAND_SLOTS_MISSED",
- .udesc = "DCT1 Command Slots Missed (in MemClks)",
- .ucode = 0x2,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3,
- .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_memory_controller_turnarounds[]={
- { .uname = "DCT0_DIMM_TURNAROUND",
- .udesc = "DCT0 DIMM (chip select) turnaround",
- .ucode = 0x1,
- },
- { .uname = "DCT0_READ_WRITE_TURNAROUND",
- .udesc = "DCT0 Read to write turnaround",
- .ucode = 0x2,
- },
- { .uname = "DCT0_WRITE_READ_TURNAROUND",
- .udesc = "DCT0 Write to read turnaround",
- .ucode = 0x4,
- },
- { .uname = "DCT1_DIMM_TURNAROUND",
- .udesc = "DCT1 DIMM (chip select) turnaround",
- .ucode = 0x8,
- },
- { .uname = "DCT1_READ_WRITE_TURNAROUND",
- .udesc = "DCT1 Read to write turnaround",
- .ucode = 0x10,
- },
- { .uname = "DCT1_WRITE_READ_TURNAROUND",
- .udesc = "DCT1 Write to read turnaround",
- .ucode = 0x20,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3f,
- .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_memory_controller_bypass_counter_saturation[]={
- { .uname = "MEMORY_CONTROLLER_HIGH_PRIORITY_BYPASS",
- .udesc = "Memory controller high priority bypass",
- .ucode = 0x1,
- },
- { .uname = "MEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASS",
- .udesc = "Memory controller medium priority bypass",
- .ucode = 0x2,
- },
- { .uname = "DCT0_DCQ_BYPASS",
- .udesc = "DCT0 DCQ bypass",
- .ucode = 0x4,
- },
- { .uname = "DCT1_DCQ_BYPASS",
- .udesc = "DCT1 DCQ bypass",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xf,
- .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_thermal_status[]={
- { .uname = "NUM_HTC_TRIP_POINT_CROSSED",
- .udesc = "Number of times the HTC trip point is crossed",
- .ucode = 0x4,
- },
- { .uname = "NUM_CLOCKS_HTC_PSTATE_INACTIVE",
- .udesc = "Number of clocks HTC P-state is inactive",
- .ucode = 0x20,
- },
- { .uname = "NUM_CLOCKS_HTC_PSTATE_ACTIVE",
- .udesc = "Number of clocks HTC P-state is active",
- .ucode = 0x40,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x64,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_cpu_io_requests_to_memory_io[]={
- { .uname = "REMOTE_IO_TO_LOCAL_IO",
- .udesc = "Remote IO to Local IO",
- .ucode = 0x61,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "REMOTE_CPU_TO_LOCAL_IO",
- .udesc = "Remote CPU to Local IO",
- .ucode = 0x64,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_IO_TO_REMOTE_IO",
- .udesc = "Local IO to Remote IO",
- .ucode = 0x91,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_IO_TO_REMOTE_MEM",
- .udesc = "Local IO to Remote Mem",
- .ucode = 0x92,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_CPU_TO_REMOTE_IO",
- .udesc = "Local CPU to Remote IO",
- .ucode = 0x94,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_CPU_TO_REMOTE_MEM",
- .udesc = "Local CPU to Remote Mem",
- .ucode = 0x98,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_IO_TO_LOCAL_IO",
- .udesc = "Local IO to Local IO",
- .ucode = 0xa1,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_IO_TO_LOCAL_MEM",
- .udesc = "Local IO to Local Mem",
- .ucode = 0xa2,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_CPU_TO_LOCAL_IO",
- .udesc = "Local CPU to Local IO",
- .ucode = 0xa4,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "LOCAL_CPU_TO_LOCAL_MEM",
- .udesc = "Local CPU to Local Mem",
- .ucode = 0xa8,
- .uflags= AMD64_FL_NCOMBO,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_cache_block_commands[]={
- { .uname = "VICTIM_BLOCK",
- .udesc = "Victim Block (Writeback)",
- .ucode = 0x1,
- },
- { .uname = "READ_BLOCK",
- .udesc = "Read Block (Dcache load miss refill)",
- .ucode = 0x4,
- },
- { .uname = "READ_BLOCK_SHARED",
- .udesc = "Read Block Shared (Icache refill)",
- .ucode = 0x8,
- },
- { .uname = "READ_BLOCK_MODIFIED",
- .udesc = "Read Block Modified (Dcache store miss refill)",
- .ucode = 0x10,
- },
- { .uname = "CHANGE_TO_DIRTY",
- .udesc = "Change-to-Dirty (first store to clean block already in cache)",
- .ucode = 0x20,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3d,
- .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_sized_commands[]={
- { .uname = "NON-POSTED_SZWR_BYTE",
- .udesc = "Non-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.",
- .ucode = 0x1,
- },
- { .uname = "NON-POSTED_SZWR_DW",
- .udesc = "Non-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1",
- .ucode = 0x2,
- },
- { .uname = "POSTED_SZWR_BYTE",
- .udesc = "Posted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; also",
- .ucode = 0x4,
- },
- { .uname = "POSTED_SZWR_DW",
- .udesc = "Posted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-line",
- .ucode = 0x8,
- },
- { .uname = "SZRD_BYTE",
- .udesc = "SzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.",
- .ucode = 0x10,
- },
- { .uname = "SZRD_DW",
- .udesc = "SzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size.",
- .ucode = 0x20,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_probe_responses_and_upstream_requests[]={
- { .uname = "PROBE_MISS",
- .udesc = "Probe miss",
- .ucode = 0x1,
- },
- { .uname = "PROBE_HIT_CLEAN",
- .udesc = "Probe hit clean",
- .ucode = 0x2,
- },
- { .uname = "PROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCEL",
- .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
- .ucode = 0x4,
- },
- { .uname = "PROBE_HIT_DIRTY_WITH_MEMORY_CANCEL",
- .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
- .ucode = 0x8,
- },
- { .uname = "UPSTREAM_DISPLAY_REFRESH_ISOC_READS",
- .udesc = "Upstream display refresh/ISOC reads",
- .ucode = 0x10,
- },
- { .uname = "UPSTREAM_NON-DISPLAY_REFRESH_READS",
- .udesc = "Upstream non-display refresh reads",
- .ucode = 0x20,
- },
- { .uname = "UPSTREAM_ISOC_WRITES",
- .udesc = "Upstream ISOC writes",
- .ucode = 0x40,
- },
- { .uname = "UPSTREAM_NON-ISOC_WRITES",
- .udesc = "Upstream non-ISOC writes",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_gart_events[]={
- { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_CPU",
- .udesc = "GART aperture hit on access from CPU",
- .ucode = 0x1,
- },
- { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_IO",
- .udesc = "GART aperture hit on access from IO",
- .ucode = 0x2,
- },
- { .uname = "GART_MISS",
- .udesc = "GART miss",
- .ucode = 0x4,
- },
- { .uname = "GART_REQUEST_HIT_TABLE_WALK_IN_PROGRESS",
- .udesc = "GART Request hit table walk in progress",
- .ucode = 0x8,
- },
- { .uname = "GART_MULTIPLE_TABLE_WALK_IN_PROGRESS",
- .udesc = "GART multiple table walk in progress",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x8f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_link_transmit_bandwidth[]={
- { .uname = "COMMAND_DW_SENT",
- .udesc = "Command DW sent",
- .ucode = 0x1,
- .grpid = 0,
- },
- { .uname = "DATA_DW_SENT",
- .udesc = "Data DW sent",
- .ucode = 0x2,
- .grpid = 0,
- },
- { .uname = "BUFFER_RELEASE_DW_SENT",
- .udesc = "Buffer release DW sent",
- .ucode = 0x4,
- .grpid = 0,
- },
- { .uname = "NOP_DW_SENT",
- .udesc = "NOP DW sent (idle)",
- .ucode = 0x8,
- .grpid = 0,
- },
- { .uname = "ADDRESS_DW_SENT",
- .udesc = "Address (including extensions) DW sent",
- .ucode = 0x10,
- .grpid = 0,
- },
- { .uname = "PER_PACKET_CRC_SENT",
- .udesc = "Per packet CRC sent",
- .ucode = 0x20,
- .grpid = 0,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- .grpid = 0,
- },
- { .uname = "SUBLINK_1",
- .udesc = "When links are unganged, enable this umask to select sublink 1",
- .ucode = 0x80,
- .grpid = 1,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "SUBLINK_0",
- .udesc = "When links are unganged, enable this umask to select sublink 0 (default when links ganged)",
- .ucode = 0x00,
- .grpid = 1,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-
-
-};
-
-static const amd64_umask_t amd64_fam15h_cpu_to_dram_requests_to_target_node[]={
- { .uname = "LOCAL_TO_NODE_0",
- .udesc = "From Local node to Node 0",
- .ucode = 0x1,
- },
- { .uname = "LOCAL_TO_NODE_1",
- .udesc = "From Local node to Node 1",
- .ucode = 0x2,
- },
- { .uname = "LOCAL_TO_NODE_2",
- .udesc = "From Local node to Node 2",
- .ucode = 0x4,
- },
- { .uname = "LOCAL_TO_NODE_3",
- .udesc = "From Local node to Node 3",
- .ucode = 0x8,
- },
- { .uname = "LOCAL_TO_NODE_4",
- .udesc = "From Local node to Node 4",
- .ucode = 0x10,
- },
- { .uname = "LOCAL_TO_NODE_5",
- .udesc = "From Local node to Node 5",
- .ucode = 0x20,
- },
- { .uname = "LOCAL_TO_NODE_6",
- .udesc = "From Local node to Node 6",
- .ucode = 0x40,
- },
- { .uname = "LOCAL_TO_NODE_7",
- .udesc = "From Local node to Node 7",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_io_to_dram_requests_to_target_node[]={
- { .uname = "LOCAL_TO_NODE_0",
- .udesc = "From Local node to Node 0",
- .ucode = 0x1,
- },
- { .uname = "LOCAL_TO_NODE_1",
- .udesc = "From Local node to Node 1",
- .ucode = 0x2,
- },
- { .uname = "LOCAL_TO_NODE_2",
- .udesc = "From Local node to Node 2",
- .ucode = 0x4,
- },
- { .uname = "LOCAL_TO_NODE_3",
- .udesc = "From Local node to Node 3",
- .ucode = 0x8,
- },
- { .uname = "LOCAL_TO_NODE_4",
- .udesc = "From Local node to Node 4",
- .ucode = 0x10,
- },
- { .uname = "LOCAL_TO_NODE_5",
- .udesc = "From Local node to Node 5",
- .ucode = 0x20,
- },
- { .uname = "LOCAL_TO_NODE_6",
- .udesc = "From Local node to Node 6",
- .ucode = 0x40,
- },
- { .uname = "LOCAL_TO_NODE_7",
- .udesc = "From Local node to Node 7",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_0_3[]={
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_0",
- .udesc = "Read block From Local node to Node 0",
- .ucode = 0x11,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_0",
- .udesc = "Read block shared From Local node to Node 0",
- .ucode = 0x12,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0",
- .udesc = "Read block modified From Local node to Node 0",
- .ucode = 0x14,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_0",
- .udesc = "Change-to-Dirty From Local node to Node 0",
- .ucode = 0x18,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_1",
- .udesc = "Read block From Local node to Node 1",
- .ucode = 0x21,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_1",
- .udesc = "Read block shared From Local node to Node 1",
- .ucode = 0x22,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1",
- .udesc = "Read block modified From Local node to Node 1",
- .ucode = 0x24,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_1",
- .udesc = "Change-to-Dirty From Local node to Node 1",
- .ucode = 0x28,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_2",
- .udesc = "Read block From Local node to Node 2",
- .ucode = 0x41,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_2",
- .udesc = "Read block shared From Local node to Node 2",
- .ucode = 0x42,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2",
- .udesc = "Read block modified From Local node to Node 2",
- .ucode = 0x44,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_2",
- .udesc = "Change-to-Dirty From Local node to Node 2",
- .ucode = 0x48,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_3",
- .udesc = "Read block From Local node to Node 3",
- .ucode = 0x81,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_3",
- .udesc = "Read block shared From Local node to Node 3",
- .ucode = 0x82,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3",
- .udesc = "Read block modified From Local node to Node 3",
- .ucode = 0x84,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_3",
- .udesc = "Change-to-Dirty From Local node to Node 3",
- .ucode = 0x88,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_4_7[]={
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_4",
- .udesc = "Read block From Local node to Node 4",
- .ucode = 0x11,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_4",
- .udesc = "Read block shared From Local node to Node 4",
- .ucode = 0x12,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4",
- .udesc = "Read block modified From Local node to Node 4",
- .ucode = 0x14,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_4",
- .udesc = "Change-to-Dirty From Local node to Node 4",
- .ucode = 0x18,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_5",
- .udesc = "Read block From Local node to Node 5",
- .ucode = 0x21,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_5",
- .udesc = "Read block shared From Local node to Node 5",
- .ucode = 0x22,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5",
- .udesc = "Read block modified From Local node to Node 5",
- .ucode = 0x24,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_5",
- .udesc = "Change-to-Dirty From Local node to Node 5",
- .ucode = 0x28,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_6",
- .udesc = "Read block From Local node to Node 6",
- .ucode = 0x41,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_6",
- .udesc = "Read block shared From Local node to Node 6",
- .ucode = 0x42,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6",
- .udesc = "Read block modified From Local node to Node 6",
- .ucode = 0x44,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_6",
- .udesc = "Change-to-Dirty From Local node to Node 6",
- .ucode = 0x48,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_LOCAL_TO_NODE_7",
- .udesc = "Read block From Local node to Node 7",
- .ucode = 0x81,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_7",
- .udesc = "Read block shared From Local node to Node 7",
- .ucode = 0x82,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7",
- .udesc = "Read block modified From Local node to Node 7",
- .ucode = 0x84,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_7",
- .udesc = "Change-to-Dirty From Local node to Node 7",
- .ucode = 0x88,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_cpu_command_requests_to_target_node[]={
- { .uname = "READ_SIZED_LOCAL_TO_NODE_0",
- .udesc = "Read Sized From Local node to Node 0",
- .ucode = 0x11,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_0",
- .udesc = "Write Sized From Local node to Node 0",
- .ucode = 0x12,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_0",
- .udesc = "Victim Block From Local node to Node 0",
- .ucode = 0x14,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_SIZED_LOCAL_TO_NODE_1",
- .udesc = "Read Sized From Local node to Node 1",
- .ucode = 0x21,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_1",
- .udesc = "Write Sized From Local node to Node 1",
- .ucode = 0x22,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_1",
- .udesc = "Victim Block From Local node to Node 1",
- .ucode = 0x24,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_SIZED_LOCAL_TO_NODE_2",
- .udesc = "Read Sized From Local node to Node 2",
- .ucode = 0x41,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_2",
- .udesc = "Write Sized From Local node to Node 2",
- .ucode = 0x42,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_2",
- .udesc = "Victim Block From Local node to Node 2",
- .ucode = 0x44,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_SIZED_LOCAL_TO_NODE_3",
- .udesc = "Read Sized From Local node to Node 3",
- .ucode = 0x81,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_3",
- .udesc = "Write Sized From Local node to Node 3",
- .ucode = 0x82,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_3",
- .udesc = "Victim Block From Local node to Node 3",
- .ucode = 0x84,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_SIZED_LOCAL_TO_NODE_4",
- .udesc = "Read Sized From Local node to Node 4",
- .ucode = 0x19,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_4",
- .udesc = "Write Sized From Local node to Node 4",
- .ucode = 0x1a,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_4",
- .udesc = "Victim Block From Local node to Node 4",
- .ucode = 0x1c,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_SIZED_LOCAL_TO_NODE_5",
- .udesc = "Read Sized From Local node to Node 5",
- .ucode = 0x29,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_5",
- .udesc = "Write Sized From Local node to Node 5",
- .ucode = 0x2a,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_5",
- .udesc = "Victim Block From Local node to Node 5",
- .ucode = 0x2c,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_SIZED_LOCAL_TO_NODE_6",
- .udesc = "Read Sized From Local node to Node 6",
- .ucode = 0x49,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_6",
- .udesc = "Write Sized From Local node to Node 6",
- .ucode = 0x4a,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_6",
- .udesc = "Victim Block From Local node to Node 6",
- .ucode = 0x4c,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "READ_SIZED_LOCAL_TO_NODE_7",
- .udesc = "Read Sized From Local node to Node 7",
- .ucode = 0x89,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "WRITE_SIZED_LOCAL_TO_NODE_7",
- .udesc = "Write Sized From Local node to Node 7",
- .ucode = 0x8a,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_7",
- .udesc = "Victim Block From Local node to Node 7",
- .ucode = 0x8c,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "ALL_LOCAL_TO_NODE_0_3",
- .udesc = "All From Local node to Node 0-3",
- .ucode = 0xf7,
- .uflags= AMD64_FL_NCOMBO,
- },
- { .uname = "ALL_LOCAL_TO_NODE_4_7",
- .udesc = "All From Local node to Node 4-7",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_request_cache_status_0[]={
- { .uname = "PROBE_HIT_S",
- .udesc = "Probe Hit S",
- .ucode = 0x1,
- },
- { .uname = "PROBE_HIT_E",
- .udesc = "Probe Hit E",
- .ucode = 0x2,
- },
- { .uname = "PROBE_HIT_MUW_OR_O",
- .udesc = "Probe Hit MuW or O",
- .ucode = 0x4,
- },
- { .uname = "PROBE_HIT_M",
- .udesc = "Probe Hit M",
- .ucode = 0x8,
- },
- { .uname = "PROBE_MISS",
- .udesc = "Probe Miss",
- .ucode = 0x10,
- },
- { .uname = "DIRECTED_PROBE",
- .udesc = "Directed Probe",
- .ucode = 0x20,
- },
- { .uname = "TRACK_CACHE_STAT_FOR_RDBLK",
- .udesc = "Track Cache Stat for RdBlk",
- .ucode = 0x40,
- },
- { .uname = "TRACK_CACHE_STAT_FOR_RDBLKS",
- .udesc = "Track Cache Stat for RdBlkS",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_request_cache_status_1[]={
- { .uname = "PROBE_HIT_S",
- .udesc = "Probe Hit S",
- .ucode = 0x1,
- },
- { .uname = "PROBE_HIT_E",
- .udesc = "Probe Hit E",
- .ucode = 0x2,
- },
- { .uname = "PROBE_HIT_MUW_OR_O",
- .udesc = "Probe Hit MuW or O",
- .ucode = 0x4,
- },
- { .uname = "PROBE_HIT_M",
- .udesc = "Probe Hit M",
- .ucode = 0x8,
- },
- { .uname = "PROBE_MISS",
- .udesc = "Probe Miss",
- .ucode = 0x10,
- },
- { .uname = "DIRECTED_PROBE",
- .udesc = "Directed Probe",
- .ucode = 0x20,
- },
- { .uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY",
- .udesc = "Track Cache Stat for ChgToDirty",
- .ucode = 0x40,
- },
- { .uname = "TRACK_CACHE_STAT_FOR_RDBLKM",
- .udesc = "Track Cache Stat for RdBlkM",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_memory_controller_requests[]={
- { .uname = "WRITE_REQUESTS_TO_DCT",
- .udesc = "Write requests sent to the DCT",
- .ucode = 0x1,
- },
- { .uname = "READ_REQUESTS_TO_DCT",
- .udesc = "Read requests (including prefetch requests) sent to the DCT",
- .ucode = 0x2,
- },
- { .uname = "PREFETCH_REQUESTS_TO_DCT",
- .udesc = "Prefetch requests sent to the DCT",
- .ucode = 0x4,
- },
- { .uname = "32_BYTES_SIZED_WRITES",
- .udesc = "32 Bytes Sized Writes",
- .ucode = 0x8,
- },
- { .uname = "64_BYTES_SIZED_WRITES",
- .udesc = "64 Bytes Sized Writes",
- .ucode = 0x10,
- },
- { .uname = "32_BYTES_SIZED_READS",
- .udesc = "32 Bytes Sized Reads",
- .ucode = 0x20,
- },
- { .uname = "64_BYTE_SIZED_READS",
- .udesc = "64 Byte Sized Reads",
- .ucode = 0x40,
- },
- { .uname = "READ_REQUESTS_TO_DCT_WHILE_WRITES_PENDING",
- .udesc = "Read requests sent to the DCT while writes requests are pending in the DCT",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_read_request_to_l3_cache[]={
- { .uname = "READ_BLOCK_EXCLUSIVE",
- .udesc = "Read Block Exclusive (Data cache read)",
- .ucode = 0x1,
- .grpid = 0,
- },
- { .uname = "READ_BLOCK_SHARED",
- .udesc = "Read Block Shared (Instruction cache read)",
- .ucode = 0x2,
- .grpid = 0,
- },
- { .uname = "READ_BLOCK_MODIFY",
- .udesc = "Read Block Modify",
- .ucode = 0x4,
- .grpid = 0,
- },
- { .uname = "PREFETCH",
- .udesc = "Count prefetches only",
- .ucode = 0x8,
- .grpid = 0,
- },
- { .uname = "READ_BLOCK_ANY",
- .udesc = "Count any read request",
- .ucode = 0x7,
- .grpid = 0,
- .uflags= AMD64_FL_DFL | AMD64_FL_NCOMBO,
- },
- CORE_SELECT(1),
-};
-
-static const amd64_umask_t amd64_fam15h_l3_fills_caused_by_l2_evictions[]={
- { .uname = "SHARED",
- .udesc = "Shared",
- .ucode = 0x1,
- .grpid = 0,
- },
- { .uname = "EXCLUSIVE",
- .udesc = "Exclusive",
- .ucode = 0x2,
- .grpid = 0,
- },
- { .uname = "OWNED",
- .udesc = "Owned",
- .ucode = 0x4,
- .grpid = 0,
- },
- { .uname = "MODIFIED",
- .udesc = "Modified",
- .ucode = 0x8,
- .grpid = 0,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- .grpid = 0,
- },
- CORE_SELECT(1),
- };
-
-static const amd64_umask_t amd64_fam15h_l3_evictions[]={
- { .uname = "SHARED",
- .udesc = "Shared",
- .ucode = 0x1,
- },
- { .uname = "EXCLUSIVE",
- .udesc = "Exclusive",
- .ucode = 0x2,
- },
- { .uname = "OWNED",
- .udesc = "Owned",
- .ucode = 0x4,
- },
- { .uname = "MODIFIED",
- .udesc = "Modified",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xf,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_l3_latency[]={
- { .uname = "L3_REQUEST_CYCLE",
- .udesc = "L3 Request cycle count.",
- .ucode = 0x1,
- },
- { .uname = "L3_REQUEST",
- .udesc = "L3 request count.",
- .ucode = 0x2,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
static const amd64_entry_t amd64_fam15h_pe[]={
{ .name = "DISPATCHED_FPU_OPS",
.desc = "FPU Pipe Assignment",
diff --git a/lib/events/amd64_events_fam15h_nb.h b/lib/events/amd64_events_fam15h_nb.h
index 82799f0..f388f59 100644
--- a/lib/events/amd64_events_fam15h_nb.h
+++ b/lib/events/amd64_events_fam15h_nb.h
@@ -99,718 +99,6 @@
.uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,\
}
-static const amd64_umask_t amd64_fam15h_nb_dispatched_fpu_ops[]={
- { .uname = "OPS_PIPE0",
- .udesc = "Total number uops assigned to Pipe 0",
- .ucode = 0x1,
- },
- { .uname = "OPS_PIPE1",
- .udesc = "Total number uops assigned to Pipe 1",
- .ucode = 0x2,
- },
- { .uname = "OPS_PIPE2",
- .udesc = "Total number uops assigned to Pipe 2",
- .ucode = 0x4,
- },
- { .uname = "OPS_PIPE3",
- .udesc = "Total number uops assigned to Pipe 3",
- .ucode = 0x8,
- },
- { .uname = "OPS_DUAL_PIPE0",
- .udesc = "Total number dual-pipe uops assigned to Pipe 0",
- .ucode = 0x10,
- },
- { .uname = "OPS_DUAL_PIPE1",
- .udesc = "Total number dual-pipe uops assigned to Pipe 1",
- .ucode = 0x20,
- },
- { .uname = "OPS_DUAL_PIPE2",
- .udesc = "Total number dual-pipe uops assigned to Pipe 2",
- .ucode = 0x40,
- },
- { .uname = "OPS_DUAL_PIPE3",
- .udesc = "Total number dual-pipe uops assigned to Pipe 3",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_retired_sse_ops[]={
- { .uname = "SINGLE_ADD_SUB_OPS",
- .udesc = "Single-precision add/subtract FLOPS",
- .ucode = 0x1,
- },
- { .uname = "SINGLE_MUL_OPS",
- .udesc = "Single-precision multiply FLOPS",
- .ucode = 0x2,
- },
- { .uname = "SINGLE_DIV_OPS",
- .udesc = "Single-precision divide/square root FLOPS",
- .ucode = 0x4,
- },
- { .uname = "SINGLE_MUL_ADD_OPS",
- .udesc = "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
- .ucode = 0x8,
- },
- { .uname = "DOUBLE_ADD_SUB_OPS",
- .udesc = "Double precision add/subtract FLOPS",
- .ucode = 0x10,
- },
- { .uname = "DOUBLE_MUL_OPS",
- .udesc = "Double precision multiply FLOPS",
- .ucode = 0x20,
- },
- { .uname = "DOUBLE_DIV_OPS",
- .udesc = "Double precision divide/square root FLOPS",
- .ucode = 0x40,
- },
- { .uname = "DOUBLE_MUL_ADD_OPS",
- .udesc = "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_move_scalar_optimization[]={
- { .uname = "SSE_MOVE_OPS",
- .udesc = "Number of SSE Move Ops",
- .ucode = 0x1,
- },
- { .uname = "SSE_MOVE_OPS_ELIM",
- .udesc = "Number of SSE Move Ops eliminated",
- .ucode = 0x2,
- },
- { .uname = "OPT_CAND",
- .udesc = "Number of Ops that are candidates for optimization (Z-bit set or pass)",
- .ucode = 0x4,
- },
- { .uname = "SCALAR_OPS_OPTIMIZED",
- .udesc = "Number of Scalar ops optimized",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xf,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_retired_serializing_ops[]={
- { .uname = "SSE_RETIRED",
- .udesc = "SSE bottom-executing uops retired",
- .ucode = 0x1,
- },
- { .uname = "SSE_MISPREDICTED",
- .udesc = "SSE control word mispredict traps due to mispredictions",
- .ucode = 0x2,
- },
- { .uname = "X87_RETIRED",
- .udesc = "X87 bottom-executing uops retired",
- .ucode = 0x4,
- },
- { .uname = "X87_MISPREDICTED",
- .udesc = "X87 control word mispredict traps due to mispredictions",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xf,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_segment_register_loads[]={
- { .uname = "ES",
- .udesc = "ES",
- .ucode = 0x1,
- },
- { .uname = "CS",
- .udesc = "CS",
- .ucode = 0x2,
- },
- { .uname = "SS",
- .udesc = "SS",
- .ucode = 0x4,
- },
- { .uname = "DS",
- .udesc = "DS",
- .ucode = 0x8,
- },
- { .uname = "FS",
- .udesc = "FS",
- .ucode = 0x10,
- },
- { .uname = "GS",
- .udesc = "GS",
- .ucode = 0x20,
- },
- { .uname = "HS",
- .udesc = "HS",
- .ucode = 0x40,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_load_q_store_q_full[]={
- { .uname = "LOAD_QUEUE",
- .udesc = "The number of cycles that the load buffer is full",
- .ucode = 0x1,
- },
- { .uname = "STORE_QUEUE",
- .udesc = "The number of cycles that the store buffer is full",
- .ucode = 0x2,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_locked_ops[]={
- { .uname = "EXECUTED",
- .udesc = "Number of locked instructions executed",
- .ucode = 0x1,
- },
- { .uname = "CYCLES_NON_SPECULATIVE_PHASE",
- .udesc = "Number of cycles spent in non-speculative phase, excluding cache miss penalty",
- .ucode = 0x4,
- },
- { .uname = "CYCLES_WAITING",
- .udesc = "Number of cycles spent in non-speculative phase, including the cache miss penalty",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xd,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_cancelled_store_to_load[]={
- { .uname = "SIZE_ADDRESS_MISMATCHES",
- .udesc = "Store is smaller than load or different starting byte but partial overlap",
- .ucode = 0x1,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x1,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_data_cache_misses[]={
- { .uname = "DC_MISS_STREAMING_STORE",
- .udesc = "First data cache miss or streaming store to a 64B cache line",
- .ucode = 0x1,
- },
- { .uname = "STREAMING_STORE",
- .udesc = "First streaming store to a 64B cache line",
- .ucode = 0x2,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_data_cache_refills_from_l2_or_northbridge[]={
- { .uname = "GOOD",
- .udesc = "Fill with good data. (Final valid status is valid)",
- .ucode = 0x1,
- },
- { .uname = "INVALID",
- .udesc = "Early valid status turned out to be invalid",
- .ucode = 0x2,
- },
- { .uname = "POISON",
- .udesc = "Fill with poison data",
- .ucode = 0x4,
- },
- { .uname = "READ_ERROR",
- .udesc = "Fill with read data error",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xf,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_unified_tlb_hit[]={
- { .uname = "4K_DATA",
- .udesc = "4 KB unified TLB hit for data",
- .ucode = 0x1,
- },
- { .uname = "2M_DATA",
- .udesc = "2 MB unified TLB hit for data",
- .ucode = 0x2,
- },
- { .uname = "1G_DATA",
- .udesc = "1 GB unified TLB hit for data",
- .ucode = 0x4,
- },
- { .uname = "4K_INST",
- .udesc = "4 KB unified TLB hit for instruction",
- .ucode = 0x10,
- },
- { .uname = "2M_INST",
- .udesc = "2 MB unified TLB hit for instruction",
- .ucode = 0x20,
- },
- { .uname = "1G_INST",
- .udesc = "1 GB unified TLB hit for instruction",
- .ucode = 0x40,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x77,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_unified_tlb_miss[]={
- { .uname = "4K_DATA",
- .udesc = "4 KB unified TLB miss for data",
- .ucode = 0x1,
- },
- { .uname = "2M_DATA",
- .udesc = "2 MB unified TLB miss for data",
- .ucode = 0x2,
- },
- { .uname = "1GB_DATA",
- .udesc = "1 GB unified TLB miss for data",
- .ucode = 0x4,
- },
- { .uname = "4K_INST",
- .udesc = "4 KB unified TLB miss for instruction",
- .ucode = 0x10,
- },
- { .uname = "2M_INST",
- .udesc = "2 MB unified TLB miss for instruction",
- .ucode = 0x20,
- },
- { .uname = "1G_INST",
- .udesc = "1 GB unified TLB miss for instruction",
- .ucode = 0x40,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x77,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_prefetch_instructions_dispatched[]={
- { .uname = "LOAD",
- .udesc = "Load (Prefetch, PrefetchT0/T1/T2)",
- .ucode = 0x1,
- },
- { .uname = "STORE",
- .udesc = "Store (PrefetchW)",
- .ucode = 0x2,
- },
- { .uname = "NTA",
- .udesc = "NTA (PrefetchNTA)",
- .ucode = 0x4,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_ineffective_sw_prefetches[]={
- { .uname = "SW_PREFETCH_HIT_IN_L1",
- .udesc = "Software prefetch hit in the L1",
- .ucode = 0x1,
- },
- { .uname = "SW_PREFETCH_HIT_IN_L2",
- .udesc = "Software prefetch hit in the L2",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x9,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_memory_requests[]={
- { .uname = "NON_CACHEABLE",
- .udesc = "Requests to non-cacheable (UC) memory",
- .ucode = 0x1,
- },
- { .uname = "WRITE_COMBINING",
- .udesc = "Requests to non-cacheable (WC, but not WC+/SS) memory",
- .ucode = 0x2,
- },
- { .uname = "STREAMING_STORE",
- .udesc = "Requests to non-cacheable (WC+/SS, but not WC) memory",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x83,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_data_prefetcher[]={
- { .uname = "ATTEMPTED",
- .udesc = "Prefetch attempts",
- .ucode = 0x2,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x2,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_mab_reqs[]={
- { .uname = "BUFFER_BIT_0",
- .udesc = "Buffer entry index bit 0",
- .ucode = 0x1,
- },
- { .uname = "BUFFER_BIT_1",
- .udesc = "Buffer entry index bit 1",
- .ucode = 0x2,
- },
- { .uname = "BUFFER_BIT_2",
- .udesc = "Buffer entry index bit 2",
- .ucode = 0x4,
- },
- { .uname = "BUFFER_BIT_3",
- .udesc = "Buffer entry index bit 3",
- .ucode = 0x8,
- },
- { .uname = "BUFFER_BIT_4",
- .udesc = "Buffer entry index bit 4",
- .ucode = 0x10,
- },
- { .uname = "BUFFER_BIT_5",
- .udesc = "Buffer entry index bit 5",
- .ucode = 0x20,
- },
- { .uname = "BUFFER_BIT_6",
- .udesc = "Buffer entry index bit 6",
- .ucode = 0x40,
- },
- { .uname = "BUFFER_BIT_7",
- .udesc = "Buffer entry index bit 7",
- .ucode = 0x80,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xff,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_system_read_responses[]={
- { .uname = "EXCLUSIVE",
- .udesc = "Exclusive",
- .ucode = 0x1,
- },
- { .uname = "MODIFIED",
- .udesc = "Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)",
- .ucode = 0x2,
- },
- { .uname = "SHARED",
- .udesc = "Shared",
- .ucode = 0x4,
- },
- { .uname = "OWNED",
- .udesc = "Owned",
- .ucode = 0x8,
- },
- { .uname = "DATA_ERROR",
- .udesc = "Data Error",
- .ucode = 0x10,
- },
- { .uname = "MODIFIED_UNWRITTEN",
- .udesc = "Modified unwritten",
- .ucode = 0x20,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_octword_write_transfers[]={
- { .uname = "OCTWORD_WRITE_TRANSFER",
- .udesc = "OW write transfer",
- .ucode = 0x1,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x1,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_requests_to_l2[]={
- { .uname = "INSTRUCTIONS",
- .udesc = "IC fill",
- .ucode = 0x1,
- },
- { .uname = "DATA",
- .udesc = "DC fill",
- .ucode = 0x2,
- },
- { .uname = "TLB_WALK",
- .udesc = "TLB fill (page table walks)",
- .ucode = 0x4,
- },
- { .uname = "SNOOP",
- .udesc = "NB probe request",
- .ucode = 0x8,
- },
- { .uname = "CANCELLED",
- .udesc = "Canceled request",
- .ucode = 0x10,
- },
- { .uname = "PREFETCHER",
- .udesc = "L2 cache prefetcher request",
- .ucode = 0x40,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x5f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_l2_cache_miss[]={
- { .uname = "INSTRUCTIONS",
- .udesc = "IC fill",
- .ucode = 0x1,
- },
- { .uname = "DATA",
- .udesc = "DC fill (includes possible replays, whereas PMCx041 does not)",
- .ucode = 0x2,
- },
- { .uname = "TLB_WALK",
- .udesc = "TLB page table walk",
- .ucode = 0x4,
- },
- { .uname = "PREFETCHER",
- .udesc = "L2 Cache Prefetcher request",
- .ucode = 0x10,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x17,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_l2_cache_fill_writeback[]={
- { .uname = "L2_FILLS",
- .udesc = "L2 fills from system",
- .ucode = 0x1,
- },
- { .uname = "L2_WRITEBACKS",
- .udesc = "L2 Writebacks to system (Clean and Dirty)",
- .ucode = 0x2,
- },
- { .uname = "L2_WRITEBACKS_CLEAN",
- .udesc = "L2 Clean Writebacks to system",
- .ucode = 0x4,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_page_splintering[]={
- { .uname = "GUEST_LARGER",
- .udesc = "Guest page size is larger than host page size when nested paging is enabled",
- .ucode = 0x1,
- },
- { .uname = "MTRR_MISMATCH",
- .udesc = "Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region",
- .ucode = 0x2,
- },
- { .uname = "HOST_LARGER",
- .udesc = "Host page size is larger than the guest page size",
- .ucode = 0x4,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_l1_itlb_miss_and_l2_itlb_miss[]={
- { .uname = "4K_PAGE_FETCHES",
- .udesc = "Instruction fetches to a 4 KB page",
- .ucode = 0x1,
- },
- { .uname = "2M_PAGE_FETCHES",
- .udesc = "Instruction fetches to a 2 MB page",
- .ucode = 0x2,
- },
- { .uname = "1G_PAGE_FETCHES",
- .udesc = "Instruction fetches to a 1 GB page",
- .ucode = 0x4,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_instruction_cache_invalidated[]={
- { .uname = "NON_SMC_PROBE_MISS",
- .udesc = "Non-SMC invalidating probe that missed on in-flight instructions",
- .ucode = 0x1,
- },
- { .uname = "NON_SMC_PROBE_HIT",
- .udesc = "Non-SMC invalidating probe that hit on in-flight instructions",
- .ucode = 0x2,
- },
- { .uname = "SMC_PROBE_MISS",
- .udesc = "SMC invalidating probe that missed on in-flight instructions",
- .ucode = 0x4,
- },
- { .uname = "SMC_PROBE_HIT",
- .udesc = "SMC invalidating probe that hit on in-flight instructions",
- .ucode = 0x8,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0xf,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_retired_mmx_fp_instructions[]={
- { .uname = "X87",
- .udesc = "X87 instructions",
- .ucode = 0x1,
- },
- { .uname = "MMX",
- .udesc = "MMX(tm) instructions",
- .ucode = 0x2,
- },
- { .uname = "SSE",
- .udesc = "SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)",
- .ucode = 0x4,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_fpu_exceptions[]={
- { .uname = "TOTAL_FAULTS",
- .udesc = "Total microfaults",
- .ucode = 0x1,
- },
- { .uname = "TOTAL_TRAPS",
- .udesc = "Total microtraps",
- .ucode = 0x2,
- },
- { .uname = "INT2EXT_FAULTS",
- .udesc = "Int2Ext faults",
- .ucode = 0x4,
- },
- { .uname = "EXT2INT_FAULTS",
- .udesc = "Ext2Int faults",
- .ucode = 0x8,
- },
- { .uname = "BYPASS_FAULTS",
- .udesc = "Bypass faults",
- .ucode = 0x10,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x1f,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_ibs_ops_tagged[]={
- { .uname = "TAGGED",
- .udesc = "Number of ops tagged by IBS",
- .ucode = 0x1,
- },
- { .uname = "RETIRED",
- .udesc = "Number of ops tagged by IBS that retired",
- .ucode = 0x2,
- },
- { .uname = "IGNORED",
- .udesc = "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired",
- .ucode = 0x4,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_ls_dispatch[]={
- { .uname = "LOADS",
- .udesc = "Loads",
- .ucode = 0x1,
- },
- { .uname = "STORES",
- .udesc = "Stores",
- .ucode = 0x2,
- },
- { .uname = "LOAD_OP_STORES",
- .udesc = "Load-op-Stores",
- .ucode = 0x4,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x7,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
-static const amd64_umask_t amd64_fam15h_nb_l2_prefetcher_trigger_events[]={
- { .uname = "LOAD_L1_MISS_SEEN_BY_PREFETCHER",
- .udesc = "Load L1 miss seen by prefetcher",
- .ucode = 0x1,
- },
- { .uname = "STORE_L1_MISS_SEEN_BY_PREFETCHER",
- .udesc = "Store L1 miss seen by prefetcher",
- .ucode = 0x2,
- },
- { .uname = "ALL",
- .udesc = "All sub-events selected",
- .ucode = 0x3,
- .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
- },
-};
-
static const amd64_umask_t amd64_fam15h_nb_dram_accesses[]={
{ .uname = "DCT0_PAGE_HIT",
.udesc = "DCT0 Page hit",
diff --git a/lib/events/intel_hswep_unc_cbo_events.h b/lib/events/intel_hswep_unc_cbo_events.h
index 22c5614..f03d5d4 100644
--- a/lib/events/intel_hswep_unc_cbo_events.h
+++ b/lib/events/intel_hswep_unc_cbo_events.h
@@ -503,29 +503,6 @@ static const intel_x86_umask_t hswep_unc_c_rxr_ismq_retry2[]={
},
};
-static const intel_x86_umask_t hswep_unc_c_rxr_occupancy[]={
- { .uname = "IPQ",
- .udesc = "IPQ",
- .ucode = 0x400,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "IRQ",
- .udesc = "IRQ",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "IRQ_REJECTED",
- .udesc = "IRQ rejected",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "VFIFO",
- .udesc = "Number of used entries in the IRQ ordering FIFO in each cycle",
- .ucode = 0x1000,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t hswep_unc_c_tor_inserts[]={
{ .uname = "OPCODE",
.udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)",
diff --git a/lib/events/intel_hswep_unc_ha_events.h b/lib/events/intel_hswep_unc_ha_events.h
index d33694f..589d5a8 100644
--- a/lib/events/intel_hswep_unc_ha_events.h
+++ b/lib/events/intel_hswep_unc_ha_events.h
@@ -25,25 +25,6 @@
* PMU: hswep_unc_ha (Intel Haswell-EP HA uncore PMU)
*/
-static const intel_x86_umask_t hswep_unc_h_conflict_cycles[]={
- { .uname = "CONFLICT",
- .udesc = "Number of cycles that we are handling conflicts",
- .ucode = 0x200,
- },
- { .uname = "LAST",
- .udesc = "Count every last conflictor in conflict chain. Can be used to compute average conflict chain length",
- .ucode = 0x400,
- },
- { .uname = "CMP_FWDS",
- .udesc = "Count the number of cmp_fwd. This gives the number of late conflicts",
- .ucode = 0x1000,
- },
- { .uname = "ACKCNFLTS",
- .udesc = "Count the number Acknflts",
- .ucode = 0x800,
- },
-};
-
static const intel_x86_umask_t hswep_unc_h_directory_lookup[]={
{ .uname = "NO_SNP",
.udesc = "Snoop not needed",
@@ -405,19 +386,6 @@ static const intel_x86_umask_t hswep_unc_h_snoop_resp[]={
},
};
-static const intel_x86_umask_t hswep_unc_h_txr_ad[]={
- { .uname = "NDR",
- .udesc = "Counts non-data responses",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SNP",
- .udesc = "Counts outbound snoops send on the ring",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t hswep_unc_h_txr_ad_cycles_full[]={
{ .uname = "ALL",
.udesc = "Counts cycles full from both schedulers",
@@ -485,58 +453,6 @@ static const intel_x86_umask_t hswep_unc_h_txr_bl[]={
},
};
-static const intel_x86_umask_t hswep_unc_h_txr_bl_cycles_full[]={
- { .uname = "ALL",
- .udesc = "BL Egress Full",
- .ucode = 0x300,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SCHED0",
- .udesc = "BL Egress Full",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SCHED1",
- .udesc = "BL Egress Full",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
-static const intel_x86_umask_t hswep_unc_h_bt_occupancy[]={
- { .uname = "LOCAL",
- .udesc = "Local",
- .ucode = 0x100,
- },
- { .uname = "REMOTE",
- .udesc = "Remote",
- .ucode = 0x200,
- },
- { .uname = "READS_REMOTE",
- .udesc = "Reads remote",
- .ucode = 0x800,
- },
- { .uname = "WRITES_LOCAL",
- .udesc = "Writes local",
- .ucode = 0x1000,
- },
- { .uname = "WRITES_REMOTE",
- .udesc = "Writes remote",
- .ucode = 0x2000,
- },
-};
-
-static const intel_x86_umask_t hswep_unc_h_bt_to_ht_not_issued[]={
- { .uname = "INCOMING_SNP_HAZARD",
- .udesc = "Number of cycles unable to issue from BT due to incoming snoop hazard",
- .ucode = 0x200,
- },
- { .uname = "INCOMING_BL_HAZARD",
- .udesc = "Number of cycles unable to issue from BT due to incoming BL data hazard",
- .ucode = 0x400,
- }
-};
-
static const intel_x86_umask_t hswep_unc_h_osb[]={
{ .uname = "REMOTE",
.udesc = "Remote",
@@ -692,18 +608,6 @@ static const intel_x86_umask_t hswep_unc_h_snoops_cycles_ne[]={
},
};
-static const intel_x86_umask_t hswep_unc_h_tracker_cycles_full[]={
- { .uname = "GP",
- .udesc = "Number of cycles when the general purpose (GP) HA tracker pool is completely used. It will not return valid count when BT is disabled",
- .ucode = 0x100,
- },
- { .uname = "ALL",
- .udesc = "Number of cycles when the general purpose (GP) HA tracker pool is completely used including reserved HT entries. It will not return vaid count when BT is disabled",
- .ucode = 0x200,
- .uflags = INTEL_X86_DFL,
- },
-};
-
static const intel_x86_umask_t hswep_unc_h_txr_ak[]={
{ .uname = "NDR",
.udesc = "Number of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socket",
@@ -719,18 +623,6 @@ static const intel_x86_umask_t hswep_unc_h_txr_ak[]={
},
};
-static const intel_x86_umask_t hswep_unc_h_iodc_conflicts[]={
- { .uname = "ANY",
- .udesc = "Any conflict",
- .ucode = 0x100,
- .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO,
- },
- { .uname = "LAST",
- .udesc = "Last conflict",
- .ucode = 0x400,
- }
-};
-
static const intel_x86_umask_t hswep_unc_h_stall_no_sbo_credit[]={
{ .uname = "SBO0_AD",
.udesc = "No credit for SBO0 AD Ring",
diff --git a/lib/events/intel_hswep_unc_irp_events.h b/lib/events/intel_hswep_unc_irp_events.h
index ceba5fc..3c2291c 100644
--- a/lib/events/intel_hswep_unc_irp_events.h
+++ b/lib/events/intel_hswep_unc_irp_events.h
@@ -25,17 +25,6 @@
* PMU: hswep_unc_irp (Intel Haswell-EP IRP uncore)
*/
-static const intel_x86_umask_t hswep_unc_i_address_match[]={
- { .uname = "STALL_COUNT",
- .udesc = "Number of time when it is not possible to merge two conflicting requests, a stall event occurs",
- .ucode = 0x100,
- },
- { .uname = "MERGE_COUNT",
- .udesc = "Number of times when two requests to the same address from the same source are received back to back, it is possible to merge them",
- .ucode = 0x200,
- },
-};
-
static const intel_x86_umask_t hswep_unc_i_cache_ack_pending_occupancy[]={
{ .uname = "ANY",
.udesc = "Any source",
@@ -48,17 +37,6 @@ static const intel_x86_umask_t hswep_unc_i_cache_ack_pending_occupancy[]={
},
};
-static const intel_x86_umask_t hswep_unc_i_tickles[]={
- { .uname = "LOST_OWNERSHIP",
- .udesc = "Number of request that lost ownership as a result of a tickle",
- .ucode = 0x100,
- },
- { .uname = "TOP_OF_QUEUE",
- .udesc = "Number of cases when a tickle was received but the request was at the head of the queue in the switch. In this case data is returned rather than releasing ownership",
- .ucode = 0x200,
- },
-};
-
static const intel_x86_umask_t hswep_unc_i_coherent_ops[]={
{ .uname = "PCIRDCUR",
.udesc = "PCI read current",
diff --git a/lib/events/intel_hswep_unc_pcu_events.h b/lib/events/intel_hswep_unc_pcu_events.h
index 1be171b..c587932 100644
--- a/lib/events/intel_hswep_unc_pcu_events.h
+++ b/lib/events/intel_hswep_unc_pcu_events.h
@@ -43,24 +43,6 @@ static const intel_x86_umask_t hswep_unc_p_power_state_occupancy[]={
},
};
-static const intel_x86_umask_t hswep_unc_p_occupancy_counters[]={
- { .uname = "C0",
- .udesc = "Counts number of cores in C0",
- .ucode = 0x0100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "C3",
- .udesc = "Counts number of cores in C3",
- .ucode = 0x0200,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "C6",
- .udesc = "Counts number of cores in C6",
- .ucode = 0x0300,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_entry_t intel_hswep_unc_p_pe[]={
{ .name = "UNC_P_CLOCKTICKS",
.desc = "PCU Uncore clockticks",
diff --git a/lib/events/intel_hswep_unc_r3qpi_events.h b/lib/events/intel_hswep_unc_r3qpi_events.h
index 8445218..409300e 100644
--- a/lib/events/intel_hswep_unc_r3qpi_events.h
+++ b/lib/events/intel_hswep_unc_r3qpi_events.h
@@ -25,24 +25,6 @@
* PMU: hswep_unc_r3qpi (Intel Haswell-EP R3QPI uncore)
*/
-static const intel_x86_umask_t hswep_unc_r3_iio_credits_acquired[]={
- { .uname = "DRS",
- .udesc = "DRS",
- .ucode = 0x800,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "NCB",
- .udesc = "NCB",
- .ucode = 0x1000,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "NCS",
- .udesc = "NCS",
- .ucode = 0x2000,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t hswep_unc_r3_ring_ad_used[]={
{ .uname = "CCW_EVEN",
.udesc = "Counter-Clockwise and even ring polarity",
@@ -151,37 +133,6 @@ static const intel_x86_umask_t hswep_unc_r3_vn0_credits_used[]={
},
};
-static const intel_x86_umask_t hswep_unc_r3_hi_ad_credits_empty[]={
- { .uname = "CBO8",
- .udesc = "CBox 8",
- .ucode = 0x100,
- },
- { .uname = "CBO9",
- .udesc = "CBox 9",
- .ucode = 0x200,
- },
- { .uname = "CBO10",
- .udesc = "CBox 10",
- .ucode = 0x400,
- },
- { .uname = "CBO11",
- .udesc = "CBox 11",
- .ucode = 0x800,
- },
- { .uname = "CBO12",
- .udesc = "CBox 12",
- .ucode = 0x1000,
- },
- { .uname = "CBO13",
- .udesc = "CBox 13",
- .ucode = 0x2000,
- },
- { .uname = "CBO14",
- .udesc = "CBox 14 & 16",
- .ucode = 0x4000,
- },
-};
-
static const intel_x86_umask_t hswep_unc_r3_c_lo_ad_credits_empty[]={
{ .uname = "CBO0",
.udesc = "CBox 0",
diff --git a/lib/events/intel_ivbep_unc_cbo_events.h b/lib/events/intel_ivbep_unc_cbo_events.h
index cd2448a..2b22f69 100644
--- a/lib/events/intel_ivbep_unc_cbo_events.h
+++ b/lib/events/intel_ivbep_unc_cbo_events.h
@@ -436,29 +436,6 @@ static const intel_x86_umask_t ivbep_unc_c_rxr_ismq_retry[]={
},
};
-static const intel_x86_umask_t ivbep_unc_c_rxr_occupancy[]={
- { .uname = "IPQ",
- .udesc = "IPQ",
- .ucode = 0x400,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "IRQ",
- .udesc = "IRQ",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "IRQ_REJECTED",
- .udesc = "IRQ rejected",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "VFIFO",
- .udesc = "Number of used entries in the IRQ ordering FIFO in each cycle",
- .ucode = 0x1000,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t ivbep_unc_c_tor_inserts[]={
{ .uname = "OPCODE",
.udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)",
diff --git a/lib/events/intel_ivbep_unc_ha_events.h b/lib/events/intel_ivbep_unc_ha_events.h
index 20beb56..60e78d2 100644
--- a/lib/events/intel_ivbep_unc_ha_events.h
+++ b/lib/events/intel_ivbep_unc_ha_events.h
@@ -308,19 +308,6 @@ static const intel_x86_umask_t ivbep_unc_h_snoop_resp[]={
},
};
-static const intel_x86_umask_t ivbep_unc_h_txr_ad[]={
- { .uname = "NDR",
- .udesc = "Counts non-data responses",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SNP",
- .udesc = "Counts outbound snoops send on the ring",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t ivbep_unc_h_txr_ad_cycles_full[]={
{ .uname = "ALL",
.udesc = "Counts cycles full from both schedulers",
@@ -388,24 +375,6 @@ static const intel_x86_umask_t ivbep_unc_h_txr_bl[]={
},
};
-static const intel_x86_umask_t ivbep_unc_h_txr_bl_cycles_full[]={
- { .uname = "ALL",
- .udesc = "BL Egress Full",
- .ucode = 0x300,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SCHED0",
- .udesc = "BL Egress Full",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SCHED1",
- .udesc = "BL Egress Full",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
#if 0
static const intel_x86_umask_t ivbep_unc_h_addr_opc_match[]={
{ .uname = "FILT",
@@ -439,17 +408,6 @@ static const intel_x86_umask_t ivbep_unc_h_bt_occupancy[]={
},
};
-static const intel_x86_umask_t ivbep_unc_h_bt_to_ht_not_issued[]={
- { .uname = "INCOMING_SNP_HAZARD",
- .udesc = "Number of cycles unable to issue from BT due to incoming snoop hazard",
- .ucode = 0x200,
- },
- { .uname = "INCOMING_BL_HAZARD",
- .udesc = "Number of cycles unable to issue from BT due to incoming BL data hazard",
- .ucode = 0x400,
- }
-};
-
static const intel_x86_umask_t ivbep_unc_h_osb[]={
{ .uname = "REMOTE",
.udesc = "Remote",
@@ -566,18 +524,6 @@ static const intel_x86_umask_t ivbep_unc_h_snp_resp_recv_local[]={
},
};
-static const intel_x86_umask_t ivbep_unc_h_tracker_cycles_full[]={
- { .uname = "GP",
- .udesc = "Number of cycles when the general purpose (GP) HA tracker pool is completely used. It will not return valid count when BT is disabled",
- .ucode = 0x100,
- },
- { .uname = "ALL",
- .udesc = "Number of cycles when the general purpose (GP) HA tracker pool is completely used including reserved HT entries. It will not return vaid count when BT is disabled",
- .ucode = 0x200,
- .uflags = INTEL_X86_DFL,
- },
-};
-
static const intel_x86_umask_t ivbep_unc_h_txr_ak[]={
{ .uname = "NDR",
.udesc = "Number of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socket",
diff --git a/lib/events/intel_ivbep_unc_pcu_events.h b/lib/events/intel_ivbep_unc_pcu_events.h
index 05b0118..ca70765 100644
--- a/lib/events/intel_ivbep_unc_pcu_events.h
+++ b/lib/events/intel_ivbep_unc_pcu_events.h
@@ -43,24 +43,6 @@ static const intel_x86_umask_t ivbep_unc_p_power_state_occupancy[]={
},
};
-static const intel_x86_umask_t ivbep_unc_p_occupancy_counters[]={
- { .uname = "C0",
- .udesc = "Counts number of cores in C0",
- .ucode = 0x0100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "C3",
- .udesc = "Counts number of cores in C3",
- .ucode = 0x0200,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "C6",
- .udesc = "Counts number of cores in C6",
- .ucode = 0x0300,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_entry_t intel_ivbep_unc_p_pe[]={
{ .name = "UNC_P_CLOCKTICKS",
.desc = "PCU Uncore clockticks",
diff --git a/lib/events/intel_ivbep_unc_r3qpi_events.h b/lib/events/intel_ivbep_unc_r3qpi_events.h
index 75cb533..c83b0d7 100644
--- a/lib/events/intel_ivbep_unc_r3qpi_events.h
+++ b/lib/events/intel_ivbep_unc_r3qpi_events.h
@@ -27,24 +27,6 @@
* PMU: ivbep_unc_r3qpi (Intel IvyBridge-EP R3QPI uncore)
*/
-static const intel_x86_umask_t ivbep_unc_r3_iio_credits_acquired[]={
- { .uname = "DRS",
- .udesc = "DRS",
- .ucode = 0x800,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "NCB",
- .udesc = "NCB",
- .ucode = 0x1000,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "NCS",
- .udesc = "NCS",
- .ucode = 0x2000,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t ivbep_unc_r3_ring_ad_used[]={
{ .uname = "CCW_VR0_EVEN",
.udesc = "Counter-Clockwise and even ring polarity on virtual ring 0",
diff --git a/lib/events/intel_snb_events.h b/lib/events/intel_snb_events.h
index 0e1034c..829f710 100644
--- a/lib/events/intel_snb_events.h
+++ b/lib/events/intel_snb_events.h
@@ -1491,25 +1491,6 @@ static const intel_x86_umask_t snb_tlb_flush[]={
},
};
-static const intel_x86_umask_t snb_uops_dispatched[]={
- { .uname = "CORE",
- .udesc = "Counts total number of uops dispatched from any thread",
- .ucode = 0x200,
- .uflags= INTEL_X86_NCOMBO,
- },
- { .uname = "STALL_CYCLES",
- .udesc = "Counts number of cycles no uops were dispatched on this thread",
- .uequiv = "THREAD:c=1:i=1",
- .ucode = 0x100 | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT),
- .uflags= INTEL_X86_NCOMBO,
- },
- { .uname = "THREAD",
- .udesc = "Counts total number of uops to be dispatched per-thread each cycle",
- .ucode = 0x100,
- .uflags= INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t snb_uops_dispatched_port[]={
{ .uname = "PORT_0",
.udesc = "Cycles which a Uop is dispatched on port 0",
diff --git a/lib/events/intel_snb_unc_events.h b/lib/events/intel_snb_unc_events.h
index 8b58926..77be5c1 100644
--- a/lib/events/intel_snb_unc_events.h
+++ b/lib/events/intel_snb_unc_events.h
@@ -134,48 +134,6 @@ static const intel_x86_umask_t snb_unc_cbo_cache_lookup[]={
},
};
-static const intel_x86_umask_t snb_unc_arb_trk_occupancy[]={
- { .uname = "ALL",
- .udesc = "Counts cycles weighted by the number of requests waiting for data returning from the memory controller, (includes coherent and non-coherent requests initiated by cores, processor graphic units, or LLC)",
- .ucode = 0x100,
- .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,
- },
-};
-
-static const intel_x86_umask_t snb_unc_arb_trk[]={
- { .uname = "ALL",
- .udesc = "Counts number of coherent and in-coherent requests initiated by cores, processor graphic units, or LLC",
- .ucode = 0x100,
- .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,
- },
- { .uname = "WRITES",
- .udesc = "Counts the number of allocated write entries, include full, partial, and LLC evictions",
- .ucode = 0x2000,
- .uflags= INTEL_X86_NCOMBO,
- },
- { .uname = "EVICTIONS",
- .udesc = "Counts the number of LLC evictions allocated",
- .ucode = 0x8000,
- .uflags= INTEL_X86_NCOMBO,
- },
-};
-
-static const intel_x86_umask_t snb_unc_arb_coh_trk_occupancy[]={
- { .uname = "ALL",
- .udesc = "Cycles weighted by number of requests pending in Coherency Tracker",
- .ucode = 0x100,
- .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,
- },
-};
-
-static const intel_x86_umask_t snb_unc_arb_coh_trk_request[]={
- { .uname = "ALL",
- .udesc = "Number of requests allocated in Coherency Tracker",
- .ucode = 0x100,
- .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,
- },
-};
-
static const intel_x86_entry_t intel_snb_unc_cbo0_pe[]={
{ .name = "UNC_CLOCKTICKS",
.desc = "uncore clock ticks",
@@ -223,34 +181,3 @@ static const intel_x86_entry_t intel_snb_unc_cbo_pe[]={
.umasks = snb_unc_cbo_cache_lookup,
},
};
-
-static const intel_x86_entry_t intel_snb_unc_arb_pe[]={
-{ .name = "UNC_ARB_TRK_OCCUPANCY",
- .desc = "ARB tracker occupancy",
- .modmsk = INTEL_SNB_UNC_ATTRS,
- .cntmsk = 0x1,
- .code = 0x80,
- .numasks = LIBPFM_ARRAY_SIZE(snb_unc_arb_trk_occupancy),
- .ngrp = 1,
- .umasks = snb_unc_arb_trk_occupancy,
-},
-{ .name = "UNC_ARB_COH_TRK_OCCUPANCY",
- .desc = "Coherency traffic occupancy",
- .modmsk = INTEL_SNB_UNC_ATTRS,
- .cntmsk = 0x1,
- .code = 0x83,
- .flags= INTEL_X86_PEBS,
- .numasks = LIBPFM_ARRAY_SIZE(snb_unc_arb_coh_trk_occupancy),
- .ngrp = 1,
- .umasks = snb_unc_arb_coh_trk_occupancy,
-},
-{ .name = "UNC_ARB_COH_TRK_REQUEST",
- .desc = "Coherency traffic requests",
- .modmsk = INTEL_SNB_UNC_ATTRS,
- .cntmsk = 0x1,
- .code = 0x84,
- .numasks = LIBPFM_ARRAY_SIZE(snb_unc_arb_coh_trk_request),
- .ngrp = 1,
- .umasks = snb_unc_arb_coh_trk_request,
-},
-};
diff --git a/lib/events/intel_snbep_unc_cbo_events.h b/lib/events/intel_snbep_unc_cbo_events.h
index 430a47c..efb38e5 100644
--- a/lib/events/intel_snbep_unc_cbo_events.h
+++ b/lib/events/intel_snbep_unc_cbo_events.h
@@ -403,29 +403,6 @@ static const intel_x86_umask_t snbep_unc_c_rxr_ismq_retry[]={
},
};
-static const intel_x86_umask_t snbep_unc_c_rxr_occupancy[]={
- { .uname = "IPQ",
- .udesc = "IPQ",
- .ucode = 0x400,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "IRQ",
- .udesc = "IRQ",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "IRQ_REJECTED",
- .udesc = "IRQ rejected",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "VFIFO",
- .udesc = "Number of used entries in the IRQ ordering FIFO in each cycle",
- .ucode = 0x1000,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
static const intel_x86_umask_t snbep_unc_c_tor_inserts[]={
{ .uname = "EVICTION",
.udesc = "Number of Evictions transactions inserted into TOR",
diff --git a/lib/events/intel_snbep_unc_ha_events.h b/lib/events/intel_snbep_unc_ha_events.h
index 68d4090..5e1ed9a 100644
--- a/lib/events/intel_snbep_unc_ha_events.h
+++ b/lib/events/intel_snbep_unc_ha_events.h
@@ -299,46 +299,6 @@ static const intel_x86_umask_t snbep_unc_h_txr_bl[]={
},
};
-static const intel_x86_umask_t snbep_unc_h_wpq_cycles_no_reg_credits[]={
- { .uname = "CHN0",
- .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "CHN1",
- .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "CHN2",
- .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular",
- .ucode = 0x400,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "CHN3",
- .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular",
- .ucode = 0x800,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
-
-static const intel_x86_umask_t snbep_unc_h_txr_bl_cycles_full[]={
- { .uname = "ALL",
- .udesc = "BL Egress Full",
- .ucode = 0x300,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SCHED0",
- .udesc = "BL Egress Full",
- .ucode = 0x100,
- .uflags = INTEL_X86_NCOMBO,
- },
- { .uname = "SCHED1",
- .udesc = "BL Egress Full",
- .ucode = 0x200,
- .uflags = INTEL_X86_NCOMBO,
- },
-};
#if 0
static const intel_x86_umask_t snbep_unc_h_addr_opc_match[]={
------------------------------------------------------------------------------
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