Hi Stephane,
attached are three patches for libpfm that I've been carrying in the
Debian packaging for some time already.
* fix inconsistent manpage sections (should be 3, even in libpfm version 4)
* add support for platforms with sizeof(time_t) != sizeof(long)
* fix typos (found by packaging tools like lintian)
Andreas
>From 5e519341fbb4da00f2433dfa638d34daa503f1d8 Mon Sep 17 00:00:00 2001
From: Andreas Beckmann <a.beckm...@fz-juelich.de>
Date: Sat, 12 Mar 2016 22:00:35 +0100
Subject: [PATCH 1/3] fix inconsistent man sections
Signed-off-by: Andreas Beckmann <a.beckm...@fz-juelich.de>
---
docs/man3/libpfm_arm_ac53.3 | 2 +-
docs/man3/libpfm_arm_ac57.3 | 2 +-
docs/man3/libpfm_arm_xgene.3 | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/man3/libpfm_arm_ac53.3 b/docs/man3/libpfm_arm_ac53.3
index 319accc..09cb779 100644
--- a/docs/man3/libpfm_arm_ac53.3
+++ b/docs/man3/libpfm_arm_ac53.3
@@ -1,4 +1,4 @@
-.TH LIBPFM 4 "May, 2014" "" "Linux Programmer's Manual"
+.TH LIBPFM 3 "May, 2014" "" "Linux Programmer's Manual"
.SH NAME
libpfm_arm_ac53 - support for ARM Cortex A53 PMU
.SH SYNOPSIS
diff --git a/docs/man3/libpfm_arm_ac57.3 b/docs/man3/libpfm_arm_ac57.3
index c471ff1..feed0b5 100644
--- a/docs/man3/libpfm_arm_ac57.3
+++ b/docs/man3/libpfm_arm_ac57.3
@@ -1,4 +1,4 @@
-.TH LIBPFM 4 "May, 2014" "" "Linux Programmer's Manual"
+.TH LIBPFM 3 "May, 2014" "" "Linux Programmer's Manual"
.SH NAME
libpfm_arm_ac57 - support for Arm Cortex A57 PMU
.SH SYNOPSIS
diff --git a/docs/man3/libpfm_arm_xgene.3 b/docs/man3/libpfm_arm_xgene.3
index a0a84bc..7f12f9e 100644
--- a/docs/man3/libpfm_arm_xgene.3
+++ b/docs/man3/libpfm_arm_xgene.3
@@ -1,4 +1,4 @@
-.TH LIBPFM 4 "May, 2014" "" "Linux Programmer's Manual"
+.TH LIBPFM 3 "May, 2014" "" "Linux Programmer's Manual"
.SH NAME
libpfm_arm_ac57 - support for Applied Micro X-Gene PMU
.SH SYNOPSIS
--
2.11.0
>From 826547fe460bdffbe9c54c29bdee19d1434023ff Mon Sep 17 00:00:00 2001
From: Andreas Beckmann <a.beckm...@fz-juelich.de>
Date: Sat, 12 Mar 2016 22:32:46 +0100
Subject: [PATCH 2/3] fix printf call with sizeof(time_t) != sizeof(long)
In environments with 32-bit long and 64-bit time_t (e.g. the x32 ABI
for x86) there is a type mismatch between the format string and its
argument. For now, always cast the timestamp to long. (Postponing this
problem until 2038 where 32-bit time_t will overflow anyway.)
Signed-off-by: Andreas Beckmann <a.beckm...@fz-juelich.de>
---
perf_examples/self_smpl_multi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/perf_examples/self_smpl_multi.c b/perf_examples/self_smpl_multi.c
index 29b6916..0ee09e3 100644
--- a/perf_examples/self_smpl_multi.c
+++ b/perf_examples/self_smpl_multi.c
@@ -165,7 +165,7 @@ do_cycles(void)
gettimeofday(&now, NULL);
if (now.tv_sec > last.tv_sec) {
printf("%ld: myid = %3d, fd = %3d, count = %4ld, iter = %4ld, rate = %ld/Kiter\n",
- now.tv_sec - start.tv_sec,
+ (long)(now.tv_sec - start.tv_sec),
myid,
fd2ov[myid].fd,
count[myid], iter[myid],
--
2.11.0
>From dd775c480ef0b278ac638627bf0242ee1ab94e98 Mon Sep 17 00:00:00 2001
From: Andreas Beckmann <a.beckm...@fz-juelich.de>
Date: Tue, 4 Apr 2017 20:53:40 +0200
Subject: [PATCH 3/3] fix some typos
Signed-off-by: Andreas Beckmann <a.beckm...@fz-juelich.de>
---
lib/events/arm_cortex_a53_events.h | 2 +-
lib/events/intel_glm_events.h | 4 ++--
lib/events/intel_hswep_unc_imc_events.h | 2 +-
lib/events/intel_ivbep_unc_imc_events.h | 2 +-
lib/events/intel_knl_events.h | 20 ++++++++++----------
lib/events/intel_knl_unc_cha_events.h | 2 +-
lib/events/power4_events.h | 4 ++--
lib/events/ppc970_events.h | 4 ++--
lib/events/ppc970mp_events.h | 4 ++--
9 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/lib/events/arm_cortex_a53_events.h b/lib/events/arm_cortex_a53_events.h
index c0d2bb6..1d769c6 100644
--- a/lib/events/arm_cortex_a53_events.h
+++ b/lib/events/arm_cortex_a53_events.h
@@ -92,7 +92,7 @@ static const arm_entry_t arm_cortex_a53_pe[]={
{.name = "BR_IMMED_RETIRED",
.modmsk = ARMV8_ATTRS,
.code = 0x0d,
- .desc = "Software chnage of the PC, instruction architecturally executed, condition check pass"
+ .desc = "Software change of the PC, instruction architecturally executed, condition check pass"
},
{.name = "UNALIGNED_LDST_RETIRED",
.modmsk = ARMV8_ATTRS,
diff --git a/lib/events/intel_glm_events.h b/lib/events/intel_glm_events.h
index 4a11b9f..65a9879 100644
--- a/lib/events/intel_glm_events.h
+++ b/lib/events/intel_glm_events.h
@@ -237,7 +237,7 @@ static const intel_x86_umask_t glm_mem_load_uops_retired[]={
.ucntmsk = 0xfull,
},
{ .uname = "HITM",
- .udesc = "Memory uop retired where cross core or cross module HITM occured (Precise Event)",
+ .udesc = "Memory uop retired where cross core or cross module HITM occurred (Precise Event)",
.ucode = 0x2000,
.uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
.grpid = 0,
@@ -268,7 +268,7 @@ static const intel_x86_umask_t glm_ld_blocks[]={
.ucntmsk = 0xfull,
},
{ .uname = "UTLB_MISS",
- .udesc = "Loads blocked because adress in not in the UTLB (Precise Event)",
+ .udesc = "Loads blocked because address in not in the UTLB (Precise Event)",
.ucode = 0x0800,
.uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
.grpid = 0,
diff --git a/lib/events/intel_hswep_unc_imc_events.h b/lib/events/intel_hswep_unc_imc_events.h
index 7f77615..8b6f4bf 100644
--- a/lib/events/intel_hswep_unc_imc_events.h
+++ b/lib/events/intel_hswep_unc_imc_events.h
@@ -165,7 +165,7 @@ static const intel_x86_umask_t hswep_unc_m_pre_count[]={
.ucode = 0x400,
},
{ .uname = "WR",
- .udesc = "Precharhe due to write",
+ .udesc = "Precharge due to write",
.ucode = 0x800,
},
{ .uname = "BYP",
diff --git a/lib/events/intel_ivbep_unc_imc_events.h b/lib/events/intel_ivbep_unc_imc_events.h
index ba60c7e..33c6c06 100644
--- a/lib/events/intel_ivbep_unc_imc_events.h
+++ b/lib/events/intel_ivbep_unc_imc_events.h
@@ -165,7 +165,7 @@ static const intel_x86_umask_t ivbep_unc_m_pre_count[]={
.ucode = 0x400,
},
{ .uname = "WR",
- .udesc = "Precharhe due to write",
+ .udesc = "Precharge due to write",
.ucode = 0x800,
},
{ .uname = "BYP",
diff --git a/lib/events/intel_knl_events.h b/lib/events/intel_knl_events.h
index d0255ba..0a69a16 100644
--- a/lib/events/intel_knl_events.h
+++ b/lib/events/intel_knl_events.h
@@ -183,7 +183,7 @@ static const intel_x86_umask_t knl_br_inst_retired[]={
static const intel_x86_umask_t knl_fetch_stall[]={
{ .uname = "ICACHE_FILL_PENDING_CYCLES",
- .udesc = "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses",
+ .udesc = "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of core cycles the fetch stalled for all icache misses",
.ucode = 0x0400,
.uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO,
},
@@ -350,22 +350,22 @@ static const intel_x86_umask_t knl_l2_rqsts[]={
static const intel_x86_umask_t knl_recycleq[]={
{ .uname = "LD_BLOCK_ST_FORWARD",
- .udesc = "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store (Precise Event).",
+ .udesc = "Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store (Precise Event).",
.ucode = 0x0100,
.uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
},
{ .uname = "LD_BLOCK_STD_NOTREADY",
- .udesc = "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready.",
+ .udesc = "Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready.",
.ucode = 0x0200,
.uflags = INTEL_X86_NCOMBO,
},
{ .uname = "ST_SPLITS",
- .udesc = "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once.",
+ .udesc = "Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once.",
.ucode = 0x0400,
.uflags = INTEL_X86_NCOMBO,
},
{ .uname = "LD_SPLITS",
- .udesc = "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once (Precise Event).",
+ .udesc = "Counts the number of occurrences a retired load that is a cache line split. Each split should be counted only once (Precise Event).",
.ucode = 0x0800,
.uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
},
@@ -560,12 +560,12 @@ static const intel_x86_umask_t knl_offcore_response_0[]={
.grpid = 1,
},
{ .uname = "L2_HIT_NEAR_TILE",
- .udesc = " accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
+ .udesc = " accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
.ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 20 | 1ULL << 19 ) << 8,
.grpid = 1,
},
{ .uname = "L2_HIT_FAR_TILE",
- .udesc = "accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
+ .udesc = "accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
.ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 22 ) << 8,
.grpid = 1,
},
@@ -746,12 +746,12 @@ static const intel_x86_umask_t knl_offcore_response_1[]={
.grpid = 1,
},
{ .uname = "L2_HIT_NEAR_TILE",
- .udesc = " accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
+ .udesc = " accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
.ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 20 | 1ULL << 19 ) << 8,
.grpid = 1,
},
{ .uname = "L2_HIT_FAR_TILE",
- .udesc = "accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
+ .udesc = "accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
.ucode = (1ULL << 36 | 1ULL << 35 | 1ULL << 22 ) << 8,
.grpid = 1,
},
@@ -1118,7 +1118,7 @@ static const intel_x86_entry_t intel_knl_pe[]={
.umasks = knl_core_reject,
},
{ .name = "RECYCLEQ",
- .desc = "Counts the number of occurences a retired load gets blocked.",
+ .desc = "Counts the number of occurrences a retired load gets blocked.",
.modmsk = INTEL_V2_ATTRS,
.cntmsk = 0x3,
.code = 0x03,
diff --git a/lib/events/intel_knl_unc_cha_events.h b/lib/events/intel_knl_unc_cha_events.h
index 11ace65..5cd401b 100644
--- a/lib/events/intel_knl_unc_cha_events.h
+++ b/lib/events/intel_knl_unc_cha_events.h
@@ -768,7 +768,7 @@ static const intel_x86_entry_t intel_knl_unc_cha_pe[]={
.umasks = knl_unc_cha_llc_victims,
},
{ .name = "UNC_H_TOR_INSERTS",
- .desc = "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
+ .desc = "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
.modmsk = KNL_UNC_CHA_TOR_ATTRS,
.cntmsk = 0xf,
.code = 0x35,
diff --git a/lib/events/power4_events.h b/lib/events/power4_events.h
index 0a2b7cc..479eac2 100644
--- a/lib/events/power4_events.h
+++ b/lib/events/power4_events.h
@@ -570,7 +570,7 @@ static const pme_power_entry_t power4_pe[] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
.pme_code = 0x926,
.pme_short_desc = "LMQ LHR merges",
- .pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
+ .pme_long_desc = "A dcache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
},
[ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
@@ -1188,7 +1188,7 @@ static const pme_power_entry_t power4_pe[] = {
.pme_name = "PM_MRK_IMR_RELOAD",
.pme_code = 0x922,
.pme_short_desc = "Marked IMR reloaded",
- .pme_long_desc = "A DL1 reload occured due to marked load",
+ .pme_long_desc = "A DL1 reload occurred due to marked load",
},
[ POWER4_PME_PM_7INST_CLB_CYC ] = {
.pme_name = "PM_7INST_CLB_CYC",
diff --git a/lib/events/ppc970_events.h b/lib/events/ppc970_events.h
index f0afff7..38cc6c4 100644
--- a/lib/events/ppc970_events.h
+++ b/lib/events/ppc970_events.h
@@ -487,7 +487,7 @@ static const pme_power_entry_t ppc970_pe[] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
.pme_code = 0x935,
.pme_short_desc = "LMQ LHR merges",
- .pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
+ .pme_long_desc = "A dcache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
},
[ PPC970_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
@@ -1039,7 +1039,7 @@ static const pme_power_entry_t ppc970_pe[] = {
.pme_name = "PM_MRK_IMR_RELOAD",
.pme_code = 0x722,
.pme_short_desc = "Marked IMR reloaded",
- .pme_long_desc = "A DL1 reload occured due to marked load",
+ .pme_long_desc = "A DL1 reload occurred due to marked load",
},
[ PPC970_PME_PM_MRK_GRP_TIMEO ] = {
.pme_name = "PM_MRK_GRP_TIMEO",
diff --git a/lib/events/ppc970mp_events.h b/lib/events/ppc970mp_events.h
index 815d196..f01f61a 100644
--- a/lib/events/ppc970mp_events.h
+++ b/lib/events/ppc970mp_events.h
@@ -514,7 +514,7 @@ static const pme_power_entry_t ppc970mp_pe[] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
.pme_code = 0x935,
.pme_short_desc = "LMQ LHR merges",
- .pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
+ .pme_long_desc = "A dcache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
},
[ PPC970MP_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
@@ -1126,7 +1126,7 @@ static const pme_power_entry_t ppc970mp_pe[] = {
.pme_name = "PM_MRK_IMR_RELOAD",
.pme_code = 0x722,
.pme_short_desc = "Marked IMR reloaded",
- .pme_long_desc = "A DL1 reload occured due to marked load",
+ .pme_long_desc = "A DL1 reload occurred due to marked load",
},
[ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = {
.pme_name = "PM_MRK_GRP_TIMEO",
--
2.11.0
------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
perfmon2-devel mailing list
perfmon2-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
