Phil, On Tue, Oct 17, 2006 at 02:55:23PM +0200, Philip J. Mucci wrote: > Hi folks, > > Attached is a patch that does a more-optimal rank based allocation of > PMU registers for MIPS. Basically assign registers with lower available > resources first. > > This will help those of you running on MIPS variants with more than 2 > counters...(keep in mind that the previous version of the kernel patch > only has support for 2.) >
Patch was added to CVS tree. I would like to mention that you need to handle the possibility of some of the PMC registers not being available. In dispatch_events() the pfmlib_input_param_t structure carries a bitmask (r_unavail_pmcs), where if a bit is set it means that the corresponding PMC is not available. Take a look at pfmlib_i386_p6.c for an example. -- -Stephane _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
