> Yes. This does not work on P6 because of the single enable bit > for all counters. It works only on AMD64 and Intel Core 2. > The P4 has other issues I have not yet solved.
Hi, Ok, I'm guessing that shouldn't P6/Perfmon disable itself in this case? There's no error thrown to the user about 'unusable PMC hardware' although I did see something in the syslog. I think create_context should fail in this case. > On Intel Core2, I will ask Andi to move the NMI to IA32_PMC1 because > even though, each counter has an individual enable bit (if you ingore the > GLOBAL_CTRL register), PEBS requires using IA32_PMC0. Ok. > > > > I noticed that there is a set of calls for implemented counters AND a > > set of calls for available counters (using the eventset). Couldn't these > > two me merged? From an application standpoint, all we care about is what > > we can use...is there ever a reason to check 'impl' when using 'avail'? > > > Are you talking about libpfm or pfm_getinfo-evtsets()? Both....it's the combination of impl from libpfm and avail from the kernel. Seems like they should be combined. Phil _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
