Phil, On Tue, Nov 07, 2006 at 06:13:08PM +0100, Philip J. Mucci wrote: > Hi Stefane, > > I've been playing around on the PPC32 box I have, in preparation for > looking at the PPC64 code. (I have a box, just not root access to the > latter.) > > I've reworked a lot of the code to resemble the MIPS code in many > ways...especially since the MIPS code is so much simpler to understand. > I've also removed the TB register from the PMD defs for now and included > skeletons for PPC970, Cell and Power4. >
I looked at some of the files and in particular asm-powerpc/perfmon.h and I have a few remarks. You cannot hardcode the mapping from PMCx to SPRN_* in pfm_arch_write_pm*(). The mapping is driven by the mapping table. As such the SPRN_* values to use must come from the table and not be in the switch() statement. This is how we do this for x86 for instance. Some of the complexity of x86 mapping comes from the P4 and hyperthreading support. But I have now duplicated the HW address of each register into the generic mapping table pfm_pmu_conf->pmc_desc[].hw_addr. You could use this instead if you ppopulate your mapping table correctly. > Anyways, attached are files for PPC32 and PPC64 support that get us a > little closer to working support. My bet is that with proper definitions > of the registers in the PPC32 file, we'll be very close to working PPC32 > support (and as such, other PPC support). I believe I sent you the name > of the machine if you want to have access...you can find my patched and > built kernel in /usr/src there. > > If I get time, I'm going to boot the kernel I built using the following > and see if I can get it to do something. > You still need some minimal libpfm support to get examples/self working... anyway, this is good progress... Thanks Phil! -- -Stephane _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
