| Hello my friend,
I am sending you two things here. One, for the problem below, the second is a patch to PPC32 and PPC64 support for Perfmon. This is a patch against the 1204 release. There were numerous updates that didn't seem to make it in from the last batch I sent in. This now builds successfully on my PPC32 on 2.6.19.1. Will be testing over the next few days.
For the assembly: I believe you can use a combination of the below.
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ppc32.patch
Description: Binary data
AND Immediate - andi. rx,ry,ui
The contents of register ry are anded with the ui and the result stored in rx. Note that in this case, the upper 16 bits of the result will be cleared because ui is a 16 bit quantity! Note that this instruction is always dotted. AND Immediate shifted - andis. rx,ry,ui
This is basically the same as andi, except the ui is shifted left 16 bits before being anded with ry, so the lower 16 bits of rx will always be cleared after this instruction.
Happy Holidays,
Phil
On Dec 19, 2006, at 9:07 AM, Stephane Eranian wrote: Hello Phil,
I am running into some issues with PPC and 2.6.20-rc1. They have introduced a new TIF bit (TIF_FREEZE) and mine are now using bit 18 and 19. The issue is that some assembly code in entry_64.S is checking a bitmask using an instruction (andi) which appears to work on 16-bit operands. I do not know PPC assembly, so it is not clear to me if this could simply be fixed by using the same instruction to work with 32-bit integers instead.
Do you know about this?
thanks. PS: any update on those IBM/AMD slides? -- -Stephane
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