Disregard this message...this one samples a different register than it overflows on. The first message re self is still valid.
Phil On Thu, 2007-01-11 at 13:13 +0100, Philip J. Mucci wrote: > Hi Stefane, > > Thanks. This is currently on a UP build. > > BTW, I have noticied similar wierdness in notify_self. The sample period > is about 1000000000 but I get: > > [EMAIL PROTECTED] ~/SVN/perf/libpfm/trunk/examples $ ./notify_self > malloc: using debugging hooks > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.367): > ev[0]=CYCLES, counters=0x3 > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.367): > ev[1]=INSNS_COMPLETE, counters=0x3 > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.450): Rank 2: > Counters available 0x3 > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.456): Rank 2: > Chose counter 0 > [CP0_25_0(pmc0)=0x18 event_mask=0x0 usr=1 os=0 sup=0 exl=0 int=1] CYCLES > [CP0_25_0(pmd0)] > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.462): 2: Used > counters 0x1 > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.450): Rank 2: > Counters available 0x2 > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.456): Rank 2: > Chose counter 1 > [CP0_25_2(pmc1)=0x118 event_mask=0x8 usr=1 os=0 sup=0 exl=0 int=1] > INSNS_COMPLETE > [CP0_25_2(pmd1)] > pfmlib_gen_mips64.c (pfm_gen_mips64_dispatch_counters.462): 2: Used > counters 0x3 > Notification 1: 833316347 INSNS_COMPLETE > Notification 2: 833315354 INSNS_COMPLETE > Notification 3: 833316243 INSNS_COMPLETE > > Phil > > On Thu, 2007-01-11 at 02:50 -0800, Stephane Eranian wrote: > > Phil, > > > > Is this on a UP or SMP build? > > If SMP, try pinning self. > > > > I will make the changes you suggested to libpfm for MIPS. > > > > On Thu, Jan 11, 2007 at 12:37:12PM +0100, Philip J. Mucci wrote: > > > Hi guys, > > > > > > It seems that an older problem has crept back in to the kernel patch. I > > > seem to remember this being fixed once before...but at the moment, it is > > > still there. > > > > > > The normal test cases inside of perfmon don't catch this case, so I have > > > included one here. Basically it's self that does multiple start and > > > stops. Manoj, Mark, can you verify this? Test case has been attached. > > > > > > One good run looks like this: > > > > > > PMD0 67073650 CYCLES > > > PMD1 53000183 INSNS_COMPLETE > > > PMD0 66098650 CYCLES > > > PMD1 53000181 INSNS_COMPLETE > > > PMD0 66094923 CYCLES > > > PMD1 53000181 INSNS_COMPLETE > > > > > > Occasionally it looks like this. Sometimes it's easier to see if you run > > > multiple copies. > > > > > > PMD0 66066007 CYCLES > > > PMD1 53000182 INSNS_COMPLETE > > > PMD0 19935908 CYCLES > > > PMD1 15730260 INSNS_COMPLETE > > > PMD0 58149463 CYCLES > > > PMD1 45930517 INSNS_COMPLETE > > > > > > I have verified this on both 64 and 32 bit builds on a MIPS 25K with an > > > unmodified (except for syscalls) patch. > > > > > > Stefane, do you have any obvious ideas about where I should look? The > > > code currently saves and restores all counters (unlike my previous > > > mails). > > > > > > --- > > > > > > BTW, the MIPS LIBPFM code I have needed some fixes for 64 bit builds as > > > well as some other minor things. > > > > > > 1) Change uint32_t to unsigned int in lib/pfmlib_gen_mips64_priv.h > > > 2) Add perfmon/pfmlib_gen_mips64.h to include/Makefile at line 92 > > > 3) Code for get_event_counters should look like this: > > > > *code = 0xff & (gen_mips64_pe[i].pme_code >> (cnt*8)); > > > Instead of: > > > < *code = 0xf & (gen_mips64_pe[i].pme_code >> (cnt*4)); > > > 4) Fix up domain bits to be 'standardized' > > > diff -r1.5 pfmlib_gen_mips64.h > > > 35,37c35,37 > > > < * PFM_PLM0 = SUPERVISOR > > > < * PFM_PLM1 = INTERRUPT > > > < * PFM_PLM2 = KERNEL > > > --- > > > > * PFM_PLM0 = KERNEL > > > > * PFM_PLM2 = INTERRUPT > > > > * PFM_PLM1 = SUPERVISOR > > > In stuff_regs: > > > < reg.sel_os = plm & PFM_PLM2 ? 1 : 0; > > > --- > > > > reg.sel_os = plm & PFM_PLM0 ? 1 : 0; > > > > reg.sel_exl = plm & PFM_PLM2 ? 1 : 0; > > > 202d227 > > > < reg.sel_exl = plm & PFM_PLM0 ? 1 : 0; > > > > > > > > > > > > > > _______________________________________________ > perfmon mailing list > [email protected] > http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/ _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
