Hi Stephane, Sorry I've been MIA for a while. :( I got pulled off the Perfmon work I was doing last summer to do some work on Cell benchmarking and tools. But now I'm back, and Carl Love and I will be working on getting Perfmon working on Cell. Carl has been working on porting oprofile to Cell, and I've been working with tools for the Cell performance counters. I've been maintaining an IBM-internal driver that someone around here wrote for accessing the hardware counters, as well as a corresponding user-space tool. But now I finally get to ditch the driver and port the tool to use the Perfmon interface instead. Yea!
So I thought I'd start out by asking if anyone has done any work on porting Perfmon to Cell. I recall that Phil made some comments last fall about working on Cell support, but I don't remember seeing anything else about it. So if anyone is already working on this, let us know and we'll lend them a hand. And since Cell is a sub-platform of powerpc, it's possible we'll be able to help get the POWER4/5/6 support finished off as well (although Cell is our first priority right now). And Carl has quite a bit of experience with the PMUs on those systems. I've also got some questions about issues that might come up during this porting effort. 1) Perfmon seems to have an implicit assumption that a PMU's counters are a fixed width. Specifically, the "pfm_pmu_config" structure has a "counter_width" field that applies to the whole PMU. However, Cell provides four 32-bit counters, and each of those can independently be configured as two 16-bit counters. So I'm curious if it will be possible to support this capability within Perfmon, especially regarding the 64-bit counter virtualization. Do you know of any other platforms that have variable-width counters? 2) Each Cell processor includes SMT support (symmetric multi-threading, basically the same as Intel hyperthreading), but only has one PMU. Unfortunately, the PMU can't be shared between two threads running simultaneously on the same CPU (unlike Intel Pentium4, which splits up the counters between the two threads when HT is enabled). Are there any mechanisms yet to prevent scheduling two threads that both want to use the PMU on the same physical CPU? This problem will also exist on POWER4/5/6. 3) In your announcement in February of the latest Perfmon kernel patches you noted that the code will not currently build on powerpc due to the new TIF flags in inclue/asm-*/thread_info.h. Has this issue been solved yet? I don't personally know much about powerpc assembly (I tried hacking around on that section of code a bit, but had no luck), but I can almost certainly track down some people here at IBM to help if we still need to find a fix. 4) After the announcement in February, there was some discussion about submitting Perfmon again to lkml. I was just wondering how close you are to posting the code. If there's anything you need help with before Perfmon can be submitted (code review, testing, cleanup, reorg, etc.), I'm happy to lend a hand. Carl and I are definitely eager to see Perfmon get included in mainline. Thanks a lot for any info you can provide. I hope to get a little more active again on this list, and we'll keep you updated as we get a bit further along with the Cell support. -- Kevin Corry [EMAIL PROTECTED] http://www.ibm.com/linux/ _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
