On Mon March 26 2007 3:02 am, Stephane Eranian wrote: > > I can see why one might want to use the 16-bit counters if it doubles the > > number of events available. However, going from 4 32-bit counters to 8 > > 16-bit counters is going to possibly cause a lot more interrupts. Double > > the number of interrupt sources and each interrupt at 2^16 times original > > the frequency. > > I would go with 4 32-bit counters. Yet I am wondering if they do not have > event restrictions which would make this difficult to hardcode. For > instance, if event A can only be measured on counter C which is only > "visible" in the 8-counter configuration.
The Cell PMU shouldn't have any restrictions like what you're describing. Each of the eight counters can connect to any of the PMU input-bus bits (which carry the event signals). However, I now remember one situation that requires the first 32-bit counter (pm0) to be used as two 16-bit counters (pm0 and pm4). There are bits in one of the "global" control registers that allow the counters to be started when pm0 overflows, and/or to be stopped when pm4 overflows. -- Kevin Corry [EMAIL PROTECTED] http://www.ibm.com/linux/ _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
