Kevin, On Mon, Mar 26, 2007 at 08:53:25AM -0500, Kevin Corry wrote: > On Sun March 25 2007 12:12 pm, Philip Mucci wrote: > > Hi folks, > > > > I think it should not be too much work to put the field with in the > > description table. With a flag, high level perfmon can just skip > > consulting this field and go with a default. > > Yeah, I had similar thoughts about how to support multiple counter sizes. It > should be relatively easy to add a counter_size field to the pfm_pmd > structure and consult that in the overflow handling code. > Yes, that is one place where the mask is used. But it is also used when we write and read PMD registers (counters). I don't know how this works on Cell, but on x86, you needs to set the upper bits of a counter for it to trigger the PMU interrupt on overflow. For that you also need to apply the counter width mask. The mask may also be used to determine which counter overflowed, unless Cell provides a bitmask for that already.
-- -Stephane _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
