On Wed, May 09, 2007 at 04:02:03PM +0200, Stéphane Zuckerman wrote:
> Of course, we didn't expect that the results would always be the same.
> We're trying to make a correlation between cache accesses/misses and
> TLB accesses/misses on this machine.
Let me start with a disclaimer that I barely understand x86_64. For ia64:
I am not sure what type of correlation you would expect. The L2 misses
will happen irrespective of TLB entries The L2 cachelines can remain
in the processor even after the TLB has been evicted. Additionally page
color effects come into play.
You might want to change the test to do more of a pointer chase thing.
It significantly reduces the cache effects as the processor has very
little chance of speculatively loading the next value. It usually shows
TLB, page color, and cache effects quite nicely.
Something like
cache_loop_init(long * array, unsigned long size)
{
unsigned long index;
for (i=0; i<size; i++) {
array[i] = gen_random_index(size);
}
}
cache_loop(long * array, unsigned long size, int loops, int read_count)
{
unsigned long index;
int current_loop;
index = gen_random_index(size);
for (current_loop = 0; current_loop < loops; current_loop++) {
for (index=0; index<read_count; index++) {
value ^= array[index];
index = array[index];
}
}
}
> As for what I deem "inconsistent": We have 4 MB of L2 cache on this
> computer for each processor, and when monitoring the whole program
> with pfmon (no --trigger-code-{start|stop}-address used) we get a few
> order of magnitude less cache misses than we predicted (according to
> the size of the data we allocated).
I can not explain the results you are seeing, but speculative loads with
a lightly contended bus could certainly be playing into this. If you
use the sample code (of course you would need to remove my code errors)
and run the loop from multiple threads at the same time, I think you
will see more L2 misses than you do now. Keep in mind that page color
issues may actually cause more L2 misses than you expect with the above
code because of the effective reduction in cache size.
Good Luck,
Robin
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