Changes to the PPC32 PMU module. This patch adds PPC32-specific routines
for the pfm_arch_pmu_info function-table.
Signed-off-by: Kevin Corry <[EMAIL PROTECTED]>
Signed-off-by: Carl Love <[EMAIL PROTECTED]>
Index: linux-2.6.22-arnd1-perfmon1/arch/powerpc/perfmon/perfmon_ppc32.c
===================================================================
--- linux-2.6.22-arnd1-perfmon1.orig/arch/powerpc/perfmon/perfmon_ppc32.c
+++ linux-2.6.22-arnd1-perfmon1/arch/powerpc/perfmon/perfmon_ppc32.c
@@ -33,10 +33,6 @@ MODULE_AUTHOR("Philip Mucci <[EMAIL PROTECTED]
MODULE_DESCRIPTION("PPC32 PMU description table");
MODULE_LICENSE("GPL");
-struct pfm_arch_pmu_info pfm_ppc32_pmu_info = {
- .pmu_style = PFM_POWERPC_PMU_NONE,
-};
-
static struct pfm_pmu_config pfm_ppc32_pmu_conf;
static struct pfm_regmap_desc pfm_ppc32_pmc_desc[] = {
@@ -181,6 +177,143 @@ static int pfm_ppc32_probe_pmu(void)
return reserve_pmc_hardware(perfmon_perf_irq);
}
+static void pfm_ppc32_write_pmc(unsigned int cnum, u64 value)
+{
+ switch (pfm_pmu_conf->pmc_desc[cnum].hw_addr) {
+ case SPRN_MMCR0:
+ mtspr(SPRN_MMCR0, value);
+ break;
+ case SPRN_MMCR1:
+ mtspr(SPRN_MMCR1, value);
+ break;
+ case SPRN_MMCR2:
+ mtspr(SPRN_MMCR2, value);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static void pfm_ppc32_write_pmd(unsigned int cnum, u64 value)
+{
+ switch (pfm_pmu_conf->pmd_desc[cnum].hw_addr) {
+ case SPRN_PMC1:
+ mtspr(SPRN_PMC1, value);
+ break;
+ case SPRN_PMC2:
+ mtspr(SPRN_PMC2, value);
+ break;
+ case SPRN_PMC3:
+ mtspr(SPRN_PMC3, value);
+ break;
+ case SPRN_PMC4:
+ mtspr(SPRN_PMC4, value);
+ break;
+ case SPRN_PMC5:
+ mtspr(SPRN_PMC5, value);
+ break;
+ case SPRN_PMC6:
+ mtspr(SPRN_PMC6, value);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static u64 pfm_ppc32_read_pmd(unsigned int cnum)
+{
+ switch (pfm_pmu_conf->pmd_desc[cnum].hw_addr) {
+ case SPRN_PMC1:
+ return mfspr(SPRN_PMC1);
+ case SPRN_PMC2:
+ return mfspr(SPRN_PMC2);
+ case SPRN_PMC3:
+ return mfspr(SPRN_PMC3);
+ case SPRN_PMC4:
+ return mfspr(SPRN_PMC4);
+ case SPRN_PMC5:
+ return mfspr(SPRN_PMC5);
+ case SPRN_PMC6:
+ return mfspr(SPRN_PMC6);
+ default:
+ BUG();
+ }
+}
+
+/**
+ * pfm_ppc32_enable_counters
+ *
+ * Just need to load the current values into the control registers.
+ **/
+static void pfm_ppc32_enable_counters(struct pfm_context *ctx,
+ struct pfm_event_set *set)
+{
+ unsigned int i, max_pmc;
+
+ max_pmc = pfm_pmu_conf->regs.max_pmc;
+
+ for (i = 0; i < max_pmc; i++)
+ if (test_bit(i, set->used_pmcs))
+ pfm_ppc32_write_pmc(i, set->pmcs[i]);
+}
+
+/**
+ * pfm_ppc32_disable_counters
+ *
+ * Just need to zero all the control registers.
+ **/
+static void pfm_ppc32_disable_counters(struct pfm_context *ctx,
+ struct pfm_event_set *set)
+{
+ unsigned int i, max;
+
+ max = pfm_pmu_conf->regs.max_pmc;
+
+ for (i = 0; i < max; i++)
+ if (test_bit(i, set->used_pmcs))
+ pfm_ppc32_write_pmc(ctx, 0);
+}
+
+/**
+ * pfm_ppc32_get_ovfl_pmds
+ *
+ * Determine which counters in this set have overflowed and fill in the
+ * set->povfl_pmds mask and set->npend_ovfls count.
+ **/
+static void pfm_ppc32_get_ovfl_pmds(struct pfm_context *ctx,
+ struct pfm_event_set *set)
+{
+ unsigned int i;
+ unsigned int max_pmd = pfm_pmu_conf->regs.max_cnt_pmd;
+ u64 *used_pmds = set->used_pmds;
+ u64 *cntr_pmds = pfm_pmu_conf->regs.cnt_pmds;
+ u64 width_mask = 1 << pfm_pmu_conf->counter_width;
+ u64 new_val, mask[PFM_PMD_BV];
+
+ bitmap_and(cast_ulp(mask), cast_ulp(cntr_pmds),
+ cast_ulp(used_pmds), max_pmd);
+
+ for (i = 0; i < max_pmd; i++) {
+ if (test_bit(i, mask)) {
+ new_val = pfm_ppc32_read_pmd(i);
+ if (new_val & width_mask) {
+ set_bit(i, set->povfl_pmds);
+ set->npend_ovfls++;
+ }
+ }
+ }
+}
+
+struct pfm_arch_pmu_info pfm_ppc32_pmu_info = {
+ .pmu_style = PFM_POWERPC_PMU_NONE,
+ .write_pmc = pfm_ppc32_write_pmc,
+ .write_pmd = pfm_ppc32_write_pmd,
+ .read_pmd = pfm_ppc32_read_pmd,
+ .get_ovfl_pmds = pfm_ppc32_get_ovfl_pmds,
+ .enable_counters = pfm_ppc32_enable_counters,
+ .disable_counters = pfm_ppc32_disable_counters,
+};
+
static struct pfm_pmu_config pfm_ppc32_pmu_conf = {
.counter_width = 31,
.pmd_desc = pfm_ppc32_pmd_desc,
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