Kevin,
I have applied this patch into my tree but there were some failure which
I corrected manually for the cbe_pmd-regs structure. I would appreciate
if you could verify that I got it right.
Thanks.
On Wed, Sep 05, 2007 at 09:14:14AM -0500, Kevin Corry wrote:
> Add register definitions to the Cell MMIO register structures that are needed
> by the Cell signal-routing patch.
>
> This is a modification of the patch posted on the cbe-oss-dev mailing list
> by Takaki Azuma ([EMAIL PROTECTED]) and Takayuki Uchikawa
> ([EMAIL PROTECTED]). Only the registers that are used by the
> new Perfmon/Cell code are included in this version.
>
> Signed-off-by: Kevin Corry <[EMAIL PROTECTED]>
> ---
>
> arch/powerpc/platforms/cell/cbe_regs.c | 27 +++++++++++++++++++++++++++
> arch/powerpc/platforms/cell/cbe_regs.h | 31 +++++++++++++++++++++++++++++--
> 2 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/platforms/cell/cbe_regs.c
> b/arch/powerpc/platforms/cell/cbe_regs.c
> index c8f7f00..f198bd6 100644
> --- a/arch/powerpc/platforms/cell/cbe_regs.c
> +++ b/arch/powerpc/platforms/cell/cbe_regs.c
> @@ -34,6 +34,7 @@ static struct cbe_regs_map
> struct cbe_iic_regs __iomem *iic_regs;
> struct cbe_mic_tm_regs __iomem *mic_tm_regs;
> struct cbe_pmd_shadow_regs pmd_shadow_regs;
> + struct cbe_ppe_priv_regs __iomem *ppe_priv_regs;
> } cbe_regs_maps[MAX_CBE];
> static int cbe_regs_map_count;
>
> @@ -146,6 +147,23 @@ struct cbe_mic_tm_regs __iomem
> *cbe_get_cpu_mic_tm_regs(int cpu)
> }
> EXPORT_SYMBOL_GPL(cbe_get_cpu_mic_tm_regs);
>
> +struct cbe_ppe_priv_regs __iomem *cbe_get_ppe_priv_regs(struct device_node
> *np)
> +{
> + struct cbe_regs_map *map = cbe_find_map(np);
> + if (map == NULL)
> + return NULL;
> + return map->ppe_priv_regs;
> +}
> +
> +struct cbe_ppe_priv_regs __iomem *cbe_get_cpu_ppe_priv_regs(int cpu)
> +{
> + struct cbe_regs_map *map = cbe_thread_map[cpu].regs;
> + if (map == NULL)
> + return NULL;
> + return map->ppe_priv_regs;
> +}
> +EXPORT_SYMBOL_GPL(cbe_get_cpu_ppe_priv_regs);
> +
> u32 cbe_get_hw_thread_id(int cpu)
> {
> return cbe_thread_map[cpu].thread_id;
> @@ -207,6 +225,11 @@ void __init cbe_fill_regs_map(struct cbe_regs_map *map)
> for_each_node_by_type(np, "mic-tm")
> if (of_get_parent(np) == be)
> map->mic_tm_regs = of_iomap(np, 0);
> +
> + for_each_node_by_type(np, "ppe-mmio")
> + if (of_get_parent(np) == be)
> + map->ppe_priv_regs = of_iomap(np, 0);
> +
> } else {
> struct device_node *cpu;
> /* That hack must die die die ! */
> @@ -228,6 +251,10 @@ void __init cbe_fill_regs_map(struct cbe_regs_map *map)
> prop = of_get_property(cpu, "mic-tm", NULL);
> if (prop != NULL)
> map->mic_tm_regs = ioremap(prop->address, prop->len);
> +
> + prop = of_get_property(cpu, "ppe-mmio", NULL);
> + if (prop != NULL)
> + map->ppe_priv_regs = ioremap(prop->address, prop->len);
> }
> }
>
> diff --git a/arch/powerpc/platforms/cell/cbe_regs.h
> b/arch/powerpc/platforms/cell/cbe_regs.h
> index 17d5971..9bac553 100644
> --- a/arch/powerpc/platforms/cell/cbe_regs.h
> +++ b/arch/powerpc/platforms/cell/cbe_regs.h
> @@ -116,7 +116,11 @@ struct cbe_pmd_regs {
> u64 fir_mode_reg; /* 0x0c18 */
> u64 fir_enable_mask; /* 0x0c20 */
>
> - u8 pad_0x0c28_0x1000 [0x1000 - 0x0c28]; /* 0x0c28 */
> + u8 pad_0x0c28_0x0c98 [0x0c98 - 0x0c28]; /* 0x0c28 */
> +
> + u64 on_ramp_trace; /* 0x0c98 */
> +
> + u64 pad_0x0ca0; /* 0x0ca0 */
> };
>
> extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
> @@ -214,7 +218,11 @@ extern struct cbe_iic_regs __iomem
> *cbe_get_cpu_iic_regs(int cpu);
>
>
> struct cbe_mic_tm_regs {
> - u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */
> + u8 pad_0x0000_0x0010[0x0010 - 0x0000]; /* 0x0000 */
> +
> + u64 MBL_debug; /* 0x0010 */
> +
> + u8 pad_0x0018_0x0040[0x0040 - 0x0018]; /* 0x0018 */
>
> u64 mic_ctl_cnfg2; /* 0x0040 */
> #define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL
> @@ -255,6 +263,25 @@ struct cbe_mic_tm_regs {
> extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct
> device_node *np);
> extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
>
> +/*
> + *
> + * PPE Privileged MMIO Registers definition. (offset 0x500000 - 0x500fff)
> + *
> + */
> +struct cbe_ppe_priv_regs {
> + u8 pad_0x0000_0x0858[0x0858 - 0x0000]; /* 0x0000 */
> +
> + u64 L2_debug1; /* 0x0858 */
> +
> + u8 pad_0x0860_0x0958[0x0958 - 0x0860]; /* 0x0860 */
> +
> + u64 ciu_dr1; /* 0x0958 */
> +
> + u8 pad_0x0960_0x1000[0x1000 - 0x0960]; /* 0x0960 */
> +};
> +
> +extern struct cbe_ppe_priv_regs __iomem *cbe_get_cpu_ppe_priv_regs(int cpu);
> +
> /* some utility functions to deal with SMT */
> extern u32 cbe_get_hw_thread_id(int cpu);
> extern u32 cbe_cpu_to_node(int cpu);
> _______________________________________________
> perfmon mailing list
> [email protected]
> http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
--
-Stephane
_______________________________________________
perfmon mailing list
[email protected]
http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
