From 1c7f1459fb21f0e2d176030094982b01db8d505f Mon Sep 17 00:00:00 2001
From: Jitka Plesnikova <jples...@redhat.com>
Date: Wed, 3 Feb 2016 16:30:55 +0100
Subject: 3.418 bump

---
 .gitignore             |  1 +
 perl-Verilog-Perl.spec | 13 ++++---------
 sources                |  2 +-
 3 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/.gitignore b/.gitignore
index 777650e..7d990dd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,3 +9,4 @@ Verilog-Perl-3.301.tar.gz
 /Verilog-Perl-3.412.tar.gz
 /Verilog-Perl-3.414.tar.gz
 /Verilog-Perl-3.416.tar.gz
+/Verilog-Perl-3.418.tar.gz
diff --git a/perl-Verilog-Perl.spec b/perl-Verilog-Perl.spec
index 4861cb4..a34a900 100644
--- a/perl-Verilog-Perl.spec
+++ b/perl-Verilog-Perl.spec
@@ -1,5 +1,5 @@
 Name:          perl-Verilog-Perl
-Version:       3.416
+Version:       3.418
 Release:       1%{?dist}
 Summary:       Verilog parsing routines
 
@@ -63,30 +63,22 @@ that use the Verilog language.
 %prep
 %setup -q -n Verilog-Perl-%{version}
 
-
 %build
 CFLAGS="%{optflags}" perl Makefile.PL INSTALLDIRS=vendor
 make %{?_smp_mflags}
 
-
 %install
 make pure_install DESTDIR=%{buildroot}
 find %{buildroot} -type f -name .packlist -exec rm -f {} ';'
 find %{buildroot} -type f -name '*.bs' -size 0 -exec rm -f {} ';'
 %{_fixperms} %{buildroot}
 
-
 %check
 # Free Electronic Lab : Package Self Test
 make test
 
-
 %files
-%if 0%{?_licensedir:1}
 %license COPYING
-%else
-%doc COPYING
-%endif
 %doc Changes README verilog/
 %dir %{perl_vendorarch}/Verilog/
 %dir %{perl_vendorarch}/auto/Verilog/
@@ -97,6 +89,9 @@ make test
 
 
 %changelog
+* Wed Feb 03 2016 Jitka Plesnikova <jples...@redhat.com> - 3.418-1
+- 3.418 bump
+
 * Thu Oct 08 2015 Jitka Plesnikova <jples...@redhat.com> - 3.416-1
 - 3.416 bump
 - Modernize spec
diff --git a/sources b/sources
index 3135729..341163a 100644
--- a/sources
+++ b/sources
@@ -1 +1 @@
-eeae6411b8fd9cdda04fea065065b2ac  Verilog-Perl-3.416.tar.gz
+77743950ce9f8f312194d4b34eed56b9  Verilog-Perl-3.418.tar.gz
-- 
cgit v0.11.2


        
http://pkgs.fedoraproject.org/cgit/perl-Verilog-Perl.git/commit/?h=master&id=1c7f1459fb21f0e2d176030094982b01db8d505f
--
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